efinix: Fix PLL with external clock input ifacewriter
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@ -295,6 +295,8 @@ design.create("{2}", "{3}", "./../gateware", overwrite=True)
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else:
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else:
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cmd += 'design.gen_pll_ref_clock("{}", pll_res="{}", refclk_src="{}", refclk_name="{}", ext_refclk_no="{}")\n\n' \
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cmd += 'design.gen_pll_ref_clock("{}", pll_res="{}", refclk_src="{}", refclk_name="{}", ext_refclk_no="{}")\n\n' \
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.format(name, block["resource"], block["input_clock"], block["input_clock_name"], block["clock_no"])
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.format(name, block["resource"], block["input_clock"], block["input_clock_name"], block["clock_no"])
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for p, val in block["input_properties"]:
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cmd += 'design.set_property("{}","{}","{}")\n'.format(block["input_clock_name"], p, val)
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else:
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else:
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cmd += 'design.gen_pll_ref_clock("{}", pll_res="{}", refclk_name="{}", refclk_src="CORE")\n'.format(name, block["resource"], block["input_signal"])
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cmd += 'design.gen_pll_ref_clock("{}", pll_res="{}", refclk_name="{}", refclk_src="CORE")\n'.format(name, block["resource"], block["input_signal"])
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cmd += 'design.set_property("{}", "CORE_CLK_PIN", "{}", block_type="PLL")\n\n'.format(name, block["input_signal"])
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cmd += 'design.set_property("{}", "CORE_CLK_PIN", "{}", block_type="PLL")\n\n'.format(name, block["input_signal"])
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@ -85,6 +85,7 @@ class EFINIXPLL(LiteXModule):
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block["input_refclk_name"] = refclk_name
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block["input_refclk_name"] = refclk_name
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block["resource"] = pll_res
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block["resource"] = pll_res
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block["clock_no"] = clock_no
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block["clock_no"] = clock_no
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block["input_properties"] = self.platform.get_pin_properties(clkin)
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self.logger.info("Clock source: {}, using EXT_CLK{}".format(block["input_clock"], clock_no))
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self.logger.info("Clock source: {}, using EXT_CLK{}".format(block["input_clock"], clock_no))
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self.platform.get_pll_resource(pll_res)
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self.platform.get_pll_resource(pll_res)
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else:
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else:
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