efinix: Fix PLL with external clock input ifacewriter

This commit is contained in:
Dolu1990 2024-08-27 09:02:58 +02:00
parent e4e9bd2125
commit 6d46a5ba05
2 changed files with 3 additions and 0 deletions

View File

@ -295,6 +295,8 @@ design.create("{2}", "{3}", "./../gateware", overwrite=True)
else: else:
cmd += 'design.gen_pll_ref_clock("{}", pll_res="{}", refclk_src="{}", refclk_name="{}", ext_refclk_no="{}")\n\n' \ cmd += 'design.gen_pll_ref_clock("{}", pll_res="{}", refclk_src="{}", refclk_name="{}", ext_refclk_no="{}")\n\n' \
.format(name, block["resource"], block["input_clock"], block["input_clock_name"], block["clock_no"]) .format(name, block["resource"], block["input_clock"], block["input_clock_name"], block["clock_no"])
for p, val in block["input_properties"]:
cmd += 'design.set_property("{}","{}","{}")\n'.format(block["input_clock_name"], p, val)
else: else:
cmd += 'design.gen_pll_ref_clock("{}", pll_res="{}", refclk_name="{}", refclk_src="CORE")\n'.format(name, block["resource"], block["input_signal"]) cmd += 'design.gen_pll_ref_clock("{}", pll_res="{}", refclk_name="{}", refclk_src="CORE")\n'.format(name, block["resource"], block["input_signal"])
cmd += 'design.set_property("{}", "CORE_CLK_PIN", "{}", block_type="PLL")\n\n'.format(name, block["input_signal"]) cmd += 'design.set_property("{}", "CORE_CLK_PIN", "{}", block_type="PLL")\n\n'.format(name, block["input_signal"])

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@ -85,6 +85,7 @@ class EFINIXPLL(LiteXModule):
block["input_refclk_name"] = refclk_name block["input_refclk_name"] = refclk_name
block["resource"] = pll_res block["resource"] = pll_res
block["clock_no"] = clock_no block["clock_no"] = clock_no
block["input_properties"] = self.platform.get_pin_properties(clkin)
self.logger.info("Clock source: {}, using EXT_CLK{}".format(block["input_clock"], clock_no)) self.logger.info("Clock source: {}, using EXT_CLK{}".format(block["input_clock"], clock_no))
self.platform.get_pll_resource(pll_res) self.platform.get_pll_resource(pll_res)
else: else: