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soc/cores/cpu/lm32: add submodule/rtl to include path (needed for lm32_include.v)

This commit is contained in:
Florent Kermarrec 2018-12-12 09:38:10 +01:00
parent 584fd51c01
commit 6d6c2b4c45
1 changed files with 1 additions and 0 deletions
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litex/soc/cores/cpu/lm32/core.py
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@ -88,6 +88,7 @@ class LM32(Module):
"lm32_debug.v", "lm32_debug.v",
"lm32_itlb.v", "lm32_itlb.v",
"lm32_dtlb.v") "lm32_dtlb.v")
platform.add_verilog_include_path(os.path.join(vdir, "submodule", "rtl"))
if variant == "minimal": if variant == "minimal":
platform.add_verilog_include_path(os.path.join(vdir, "config_minimal")) platform.add_verilog_include_path(os.path.join(vdir, "config_minimal"))
elif variant == "lite": elif variant == "lite":