CHANGES: Update.

2022-01-31 17:00:12 +01:00 · 2022-01-31 17:00:12 +01:00 · 6f6a10db5c
parent 0711998dab
commit 6f6a10db5c
1 changed files with 4 additions and 0 deletions
--- a/4
+++ b/4
@ -21,6 +21,10 @@
 	- litex_sim:          Add .json support for --rom/ram/sdram-init.
 	- soc/add_uart:       Allow multiple UARTs in the same design.
 	- cores/cpu:          Add out-of-tree support.
+	- build/xilinx:       Add initial Yosys/NextPnr support on Artix7 (and Zynq7000 with Artix7 fabric).
+	- add_source:         Add optional copy to gateware directory.
+	- cores/jtag:         Add initial JTAG-UART/JTAGBone Altera/Intel support.
+	- LiteScope:          Add Samplerate support.

    [> API changes/Deprecation
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