examples: Wishbone interconnect test bench
This commit is contained in:
Sebastien Bourdeauducq
parent
c840848dba
commit
6f7a35e0a3
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SOURCES=tb_intercon.v intercon.v master.v slave.v
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all: tb_intercon
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sim: tb_intercon
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./tb_intercon
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cversim: $(SOURCES)
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cver $(SOURCES)
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clean:
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rm -f tb_intercon intercon.v intercon.vcd verilog.log
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tb_intercon: $(SOURCES)
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iverilog -o tb_intercon $(SOURCES)
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intercon.v: intercon_conv.py
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python3 intercon_conv.py > intercon.v
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.PHONY: clean sim cversim
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from migen.fhdl import verilog
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from migen.fhdl import structure as f
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from migen.bus import wishbone
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m1 = wishbone.Master("m1")
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m2 = wishbone.Master("m2")
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s1 = wishbone.Slave("s1")
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s2 = wishbone.Slave("s2")
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wishbonecon0 = wishbone.InterconnectShared(
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[m1, m2],
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[(0, s1), (1, s2)],
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register=True,
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offset=1)
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frag = wishbonecon0.GetFragment()
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v = verilog.Convert(frag, name="intercon", ios={m1.cyc_o, m1.stb_o, m1.we_o, m1.adr_o, m1.sel_o, m1.dat_o, m1.dat_i, m1.ack_i,
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m2.cyc_o, m2.stb_o, m2.we_o, m2.adr_o, m2.sel_o, m2.dat_o, m2.dat_i, m2.ack_i,
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s1.cyc_i, s1.stb_i, s1.we_i, s1.adr_i, s1.sel_i, s1.dat_i, s1.dat_o, s1.ack_o,
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s2.cyc_i, s2.stb_i, s2.we_i, s2.adr_i, s2.sel_i, s2.dat_i, s2.dat_o, s2.ack_o})
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print(v)
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/*
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* Milkymist SoC
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* Copyright (C) 2007, 2008, 2009, 2011 Sebastien Bourdeauducq
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, version 3 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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module master #(
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parameter id = 0,
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parameter nreads = 10,
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parameter nwrites = 10,
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parameter p = 4
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) (
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input sys_clk,
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input sys_rst,
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output reg [31:0] dat_w,
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input [31:0] dat_r,
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output reg [31:0] adr,
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output reg we,
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output reg [3:0] sel,
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output cyc,
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output stb,
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input ack,
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output reg tend
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);
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integer rcounter;
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integer wcounter;
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reg active;
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assign cyc = active;
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assign stb = active;
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always @(posedge sys_clk) begin
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if(sys_rst) begin
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dat_w <= 0;
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adr <= 0;
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we <= 0;
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sel <= 0;
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active <= 0;
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rcounter = 0;
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wcounter = 0;
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tend <= 0;
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end else begin
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if(ack) begin
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if(~active)
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$display("[M%d] Spurious ack", id);
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else begin
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if(we)
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$display("[M%d] Ack W: %x:%x [%x]", id, adr, dat_w, sel);
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else
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$display("[M%d] Ack R: %x:%x [%x]", id, adr, dat_r, sel);
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end
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active <= 1'b0;
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end else if(~active) begin
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if(($random % p) == 0) begin
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adr <= (($random % 5)<< (32-2)) + id;
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sel <= sel + 1;
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active <= 1'b1;
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if(($random % 2) == 0) begin
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/* Read */
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we <= 1'b0;
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rcounter = rcounter + 1;
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end else begin
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/* Write */
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we <= 1'b1;
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dat_w <= ($random << 16) + id;
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wcounter = wcounter + 1;
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end
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end
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end
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tend <= (rcounter >= nreads) && (wcounter >= nwrites);
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end
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end
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endmodule
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@ -0,0 +1,55 @@
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/*
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* Milkymist SoC
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* Copyright (C) 2007, 2008, 2009, 2011 Sebastien Bourdeauducq
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, version 3 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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module slave #(
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parameter id = 0,
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parameter p = 3
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) (
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input sys_clk,
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input sys_rst,
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input [31:0] dat_w,
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output reg [31:0] dat_r,
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input [31:0] adr,
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input we,
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input [3:0] sel,
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input cyc,
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input stb,
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output reg ack
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);
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always @(posedge sys_clk) begin
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if(sys_rst) begin
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dat_r <= 0;
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ack <= 0;
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end else begin
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if(cyc & stb & ~ack) begin
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if(($random % p) == 0) begin
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ack <= 1;
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if(~we)
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dat_r <= ($random << 16) + id;
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if(we)
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$display("[S%d] Ack W: %x:%x [%x]", id, adr, dat_w, sel);
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else
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$display("[S%d] Ack R: %x:%x [%x]", id, adr, dat_r, sel);
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end
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end else
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ack <= 0;
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end
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end
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endmodule
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@ -0,0 +1,214 @@
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/*
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* Milkymist SoC
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* Copyright (C) 2007, 2008, 2009, 2011 Sebastien Bourdeauducq
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, version 3 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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module tb_conbus();
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reg sys_rst;
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reg sys_clk;
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//------------------------------------------------------------------
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// Wishbone master wires
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//------------------------------------------------------------------
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wire [31:0] wishbone_m1_adr,
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wishbone_m2_adr;
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wire [31:0] wishbone_m1_dat_r,
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wishbone_m1_dat_w,
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wishbone_m2_dat_r,
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wishbone_m2_dat_w;
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wire [3:0] wishbone_m1_sel,
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wishbone_m2_sel;
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wire wishbone_m1_we,
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wishbone_m2_we;
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wire wishbone_m1_cyc,
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wishbone_m2_cyc;
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wire wishbone_m1_stb,
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wishbone_m2_stb;
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wire wishbone_m1_ack,
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wishbone_m2_ack;
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//------------------------------------------------------------------
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// Wishbone slave wires
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//------------------------------------------------------------------
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wire [31:0] wishbone_s1_adr,
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wishbone_s2_adr;
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wire [31:0] wishbone_s1_dat_r,
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wishbone_s1_dat_w,
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wishbone_s2_dat_r,
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wishbone_s2_dat_w;
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wire [3:0] wishbone_s1_sel,
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wishbone_s2_sel;
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wire wishbone_s1_we,
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wishbone_s2_we;
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wire wishbone_s1_cyc,
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wishbone_s2_cyc;
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wire wishbone_s1_stb,
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wishbone_s2_stb;
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wire wishbone_s1_ack,
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wishbone_s2_ack;
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//---------------------------------------------------------------------------
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// Wishbone switch
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//---------------------------------------------------------------------------
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intercon dut(
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.sys_clk(sys_clk),
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.sys_rst(sys_rst),
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// Master 0
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.wishbone_m1_dat_o(wishbone_m1_dat_w),
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.wishbone_m1_dat_i(wishbone_m1_dat_r),
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.wishbone_m1_adr_o(wishbone_m1_adr),
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.wishbone_m1_we_o(wishbone_m1_we),
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.wishbone_m1_sel_o(wishbone_m1_sel),
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.wishbone_m1_cyc_o(wishbone_m1_cyc),
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.wishbone_m1_stb_o(wishbone_m1_stb),
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.wishbone_m1_ack_i(wishbone_m1_ack),
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// Master 1
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.wishbone_m2_dat_o(wishbone_m2_dat_w),
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.wishbone_m2_dat_i(wishbone_m2_dat_r),
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.wishbone_m2_adr_o(wishbone_m2_adr),
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.wishbone_m2_we_o(wishbone_m2_we),
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.wishbone_m2_sel_o(wishbone_m2_sel),
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.wishbone_m2_cyc_o(wishbone_m2_cyc),
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.wishbone_m2_stb_o(wishbone_m2_stb),
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.wishbone_m2_ack_i(wishbone_m2_ack),
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// Slave 0
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.wishbone_s1_dat_o(wishbone_s1_dat_r),
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.wishbone_s1_dat_i(wishbone_s1_dat_w),
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.wishbone_s1_adr_i(wishbone_s1_adr),
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.wishbone_s1_sel_i(wishbone_s1_sel),
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.wishbone_s1_we_i(wishbone_s1_we),
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.wishbone_s1_cyc_i(wishbone_s1_cyc),
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.wishbone_s1_stb_i(wishbone_s1_stb),
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.wishbone_s1_ack_o(wishbone_s1_ack),
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// Slave 1
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.wishbone_s2_dat_o(wishbone_s2_dat_r),
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.wishbone_s2_dat_i(wishbone_s2_dat_w),
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.wishbone_s2_adr_i(wishbone_s2_adr),
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.wishbone_s2_sel_i(wishbone_s2_sel),
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.wishbone_s2_we_i(wishbone_s2_we),
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.wishbone_s2_cyc_i(wishbone_s2_cyc),
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.wishbone_s2_stb_i(wishbone_s2_stb),
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.wishbone_s2_ack_o(wishbone_s2_ack)
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);
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//---------------------------------------------------------------------------
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// Masters
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//---------------------------------------------------------------------------
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wire wishbone_m1_end;
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master #(
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.id(0)
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) m0 (
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.sys_clk(sys_clk),
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.sys_rst(sys_rst),
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.dat_w(wishbone_m1_dat_w),
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.dat_r(wishbone_m1_dat_r),
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.adr(wishbone_m1_adr),
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.we(wishbone_m1_we),
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.sel(wishbone_m1_sel),
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.cyc(wishbone_m1_cyc),
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.stb(wishbone_m1_stb),
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.ack(wishbone_m1_ack),
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.tend(wishbone_m1_end)
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);
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wire wishbone_m2_end;
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master #(
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.id(1)
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) m1 (
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.sys_clk(sys_clk),
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.sys_rst(sys_rst),
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.dat_w(wishbone_m2_dat_w),
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.dat_r(wishbone_m2_dat_r),
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.adr(wishbone_m2_adr),
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.we(wishbone_m2_we),
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.sel(wishbone_m2_sel),
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.cyc(wishbone_m2_cyc),
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.stb(wishbone_m2_stb),
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.ack(wishbone_m2_ack),
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.tend(wishbone_m2_end)
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);
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//---------------------------------------------------------------------------
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// Slaves
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//---------------------------------------------------------------------------
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slave #(
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.id(0)
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) s0 (
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.sys_clk(sys_clk),
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.sys_rst(sys_rst),
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.dat_w(wishbone_s1_dat_w),
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.dat_r(wishbone_s1_dat_r),
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.adr(wishbone_s1_adr),
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.we(wishbone_s1_we),
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.sel(wishbone_s1_sel),
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.cyc(wishbone_s1_cyc),
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.stb(wishbone_s1_stb),
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.ack(wishbone_s1_ack)
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);
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slave #(
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.id(1)
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) s1 (
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.sys_clk(sys_clk),
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.sys_rst(sys_rst),
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.dat_w(wishbone_s2_dat_w),
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.dat_r(wishbone_s2_dat_r),
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.adr(wishbone_s2_adr),
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.we(wishbone_s2_we),
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.sel(wishbone_s2_sel),
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.cyc(wishbone_s2_cyc),
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.stb(wishbone_s2_stb),
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.ack(wishbone_s2_ack)
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);
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initial sys_clk = 1'b0;
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always #5 sys_clk = ~sys_clk;
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wire all_end = wishbone_m1_end & wishbone_m2_end;
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always begin
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$dumpfile("intercon.vcd");
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$dumpvars(1, dut);
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sys_rst = 1'b1;
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@(posedge sys_clk);
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#1 sys_rst = 1'b0;
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@(posedge all_end);
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$finish;
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end
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endmodule
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