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sim: support for signed numbers

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This commit is contained in:
Sebastien Bourdeauducq 2012-03-06 16:46:18 +01:00
parent 90184b22d2
commit 6f829c7afc
2 changed files with 10 additions and 5 deletions
examples
basic_sim.py
migen/sim
generic.py

4
examples/basic_sim.py
View file

@ -5,7 +5,7 @@ from migen.sim.icarus import Runner
class Counter: class Counter:
def __init__(self): def __init__(self):
self.ce = Signal() self.ce = Signal()
self.count = Signal(BV(4)) self.count = Signal(BV(37, True), reset=-5)
def do_simulation(self, s, cycle): def do_simulation(self, s, cycle):
if cycle % 2: if cycle % 2:
@ -22,6 +22,6 @@ class Counter:
def main(): def main():
dut = Counter() dut = Counter()
sim = Simulator(dut.get_fragment(), Runner(), TopLevel("my.vcd")) sim = Simulator(dut.get_fragment(), Runner(), TopLevel("my.vcd"))
sim.run(10) sim.run(20)
main() main()

11
migen/sim/generic.py
View file

@ -111,12 +111,17 @@ class Simulator:
self.ipc.send(MessageRead(name)) self.ipc.send(MessageRead(name))
reply = self.ipc.recv() reply = self.ipc.recv()
assert(isinstance(reply, MessageReadReply)) assert(isinstance(reply, MessageReadReply))
# TODO: negative numbers + cleanup LSBs nbits = signal.bv.width
return reply.value value = reply.value & (2**nbits - 1)
if signal.bv.signed and (value & 2**(nbits - 1)):
value -= 2**nbits
return value
def wr(self, signal, value): def wr(self, signal, value):
name = self.top_level.top_name + "." \ name = self.top_level.top_name + "." \
+ self.top_level.dut_name + "." \ + self.top_level.dut_name + "." \
+ self.namespace.get_name(signal) + self.namespace.get_name(signal)
# TODO: negative numbers if value < 0:
value += 2**signal.bv.width
assert(value >= 0 and value < 2**signal.bv.width)
self.ipc.send(MessageWrite(name, value)) self.ipc.send(MessageWrite(name, value))