fhdl/verilog: fix signed constant conversion

2012-03-06 16:45:44 +01:00 · 2012-03-06 16:45:44 +01:00 · 90184b22d2
parent 0a23cadd38
commit 90184b22d2
1 changed files with 1 additions and 1 deletions
--- a/migen/fhdl/verilog.py
+++ b/migen/fhdl/verilog.py
@ -21,7 +21,7 @@ def _printexpr(ns, node):
 		if node.n >= 0:
 			return str(node.bv) + str(node.n)
 		else:
-			return "-" + str(node.bv) + str(-self.n)
+			return "-" + str(node.bv) + str(-node.n)
 	elif isinstance(node, Signal):
 		return ns.get_name(node)
 	elif isinstance(node, _Operator):