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add ternary operator sel ? a : b

This commit is contained in:
Nina Engelhardt 2013-08-11 23:53:33 +02:00 committed by Sebastien Bourdeauducq
parent e12187aa80
commit 6f9f08f6eb
2 changed files with 13 additions and 0 deletions
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3
migen/fhdl/structure.py
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@ -94,6 +94,9 @@ class _Operator(Value):
self.op = op self.op = op
self.operands = operands self.operands = operands
def Mux(sel, val1, val0):
return _Operator("m", [sel, val1, val0])
class _Slice(Value): class _Slice(Value):
def __init__(self, value, start, stop): def __init__(self, value, start, stop):
Value.__init__(self) Value.__init__(self)

10
migen/fhdl/verilog.py
View File

@ -58,6 +58,16 @@ def _printexpr(ns, node):
r2 = "$signed({1'd0, " + r2 + "})" r2 = "$signed({1'd0, " + r2 + "})"
r = r1 + " " + node.op + " " + r2 r = r1 + " " + node.op + " " + r2
s = s1 or s2 s = s1 or s2
elif arity == 3:
assert node.op == "m"
r2, s2 = _printexpr(ns, node.operands[1])
r3, s3 = _printexpr(ns, node.operands[2])
if s2 and not s3:
r3 = "$signed({1'd0, " + r3 + "})"
if s3 and not s2:
r2 = "$signed({1'd0, " + r2 + "})"
r = r1 + " ? " + r2 + " : " + r3
s = s2 or s3
else: else:
raise TypeError raise TypeError
return "(" + r + ")", s return "(" + r + ")", s