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soc_core: use cpu.data_width to compute csr_alignment (and remove Rocket workaround)

This commit is contained in:
Florent Kermarrec 2019-09-29 15:47:10 +02:00
parent b826c1705f
commit 6fcb12a98f
1 changed files with 7 additions and 10 deletions
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17
litex/soc/integration/soc_core.py
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@ -124,10 +124,6 @@ class SoCCore(Module):
if cpu_type == "None": if cpu_type == "None":
cpu_type = None cpu_type = None
# FIXME: On RocketChip, CSRs *must* be 64-bit aligned.
if cpu_type == "rocket":
csr_alignment = 64
if not with_wishbone: if not with_wishbone:
self.soc_mem_map["csr"] = 0x00000000 self.soc_mem_map["csr"] = 0x00000000
@ -142,10 +138,8 @@ class SoCCore(Module):
self.integrated_main_ram_size = integrated_main_ram_size self.integrated_main_ram_size = integrated_main_ram_size
assert csr_data_width in [8, 32, 64] assert csr_data_width in [8, 32, 64]
assert csr_alignment in [32, 64]
assert 2**(csr_address_width + 2) <= 0x1000000 assert 2**(csr_address_width + 2) <= 0x1000000
self.csr_data_width = csr_data_width self.csr_data_width = csr_data_width
self.csr_alignment = csr_alignment
self.csr_address_width = csr_address_width self.csr_address_width = csr_address_width
self.with_ctrl = with_ctrl self.with_ctrl = with_ctrl
@ -252,13 +246,16 @@ class SoCCore(Module):
self.add_interrupt("timer0", allow_user_defined=True) self.add_interrupt("timer0", allow_user_defined=True)
# Add Wishbone to CSR bridge # Add Wishbone to CSR bridge
self.config["CSR_DATA_WIDTH"] = self.csr_data_width csr_alignment = max(csr_alignment, self.cpu.data_width)
self.config["CSR_ALIGNMENT"] = self.csr_alignment self.config["CSR_DATA_WIDTH"] = csr_data_width
self.config["CSR_ALIGNMENT"] = csr_alignment
self.csr_data_width = csr_data_width
self.csr_alignment = csr_alignment
if with_wishbone: if with_wishbone:
self.submodules.wishbone2csr = wishbone2csr.WB2CSR( self.submodules.wishbone2csr = wishbone2csr.WB2CSR(
bus_csr=csr_bus.Interface( bus_csr=csr_bus.Interface(
address_width=self.csr_address_width, address_width = csr_address_width,
data_width=self.csr_data_width)) data_width = csr_data_width))
self.add_csr_master(self.wishbone2csr.csr) self.add_csr_master(self.wishbone2csr.csr)
self.register_mem("csr", self.soc_mem_map["csr"], self.wishbone2csr.wishbone, 0x1000000) self.register_mem("csr", self.soc_mem_map["csr"], self.wishbone2csr.wishbone, 0x1000000)