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litex
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Use meaningful class names

This commit is contained in:
Sebastien Bourdeauducq 2012-01-21 12:25:22 +01:00
parent f6aa95a4d0
commit 6fde54c5aa
6 changed files with 12 additions and 12 deletions
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2
milkymist/clkfx/__init__.py
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@ -2,7 +2,7 @@ from fractions import Fraction
from migen.fhdl.structure import * from migen.fhdl.structure import *
class Inst: class ClkFX:
def __init__(self, infreq, outfreq): def __init__(self, infreq, outfreq):
self.clkin = Signal() self.clkin = Signal()
self.clkout = Signal() self.clkout = Signal()

2
milkymist/lm32/__init__.py
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@ -1,7 +1,7 @@
from migen.fhdl.structure import * from migen.fhdl.structure import *
from migen.bus import wishbone from migen.bus import wishbone
class Inst: class LM32:
def __init__(self): def __init__(self):
self.ibus = i = wishbone.Master("lm32i") self.ibus = i = wishbone.Master("lm32i")
self.dbus = d = wishbone.Master("lm32d") self.dbus = d = wishbone.Master("lm32d")

2
milkymist/m1reset/__init__.py
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@ -1,6 +1,6 @@
from migen.fhdl.structure import * from migen.fhdl.structure import *
class Inst: class M1Reset:
def __init__(self): def __init__(self):
self.trigger_reset = Signal() self.trigger_reset = Signal()
self.sys_rst = Signal() self.sys_rst = Signal()

4
milkymist/norflash/__init__.py
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@ -2,7 +2,7 @@ from migen.fhdl.structure import *
from migen.bus import wishbone from migen.bus import wishbone
from migen.corelogic import timeline from migen.corelogic import timeline
class Inst: class NorFlash:
def __init__(self, adr_width, rd_timing): def __init__(self, adr_width, rd_timing):
self.bus = wishbone.Slave("norflash") self.bus = wishbone.Slave("norflash")
self.adr = Signal(BV(adr_width-1)) self.adr = Signal(BV(adr_width-1))
@ -10,7 +10,7 @@ class Inst:
self.oe_n = Signal() self.oe_n = Signal()
self.we_n = Signal() self.we_n = Signal()
self.ce_n = Signal() self.ce_n = Signal()
self.timeline = timeline.Inst(self.bus.cyc_i & self.bus.stb_i, self.timeline = timeline.Timeline(self.bus.cyc_i & self.bus.stb_i,
[(0, [self.adr.eq(Cat(0, self.bus.adr_i[:adr_width-2]))]), [(0, [self.adr.eq(Cat(0, self.bus.adr_i[:adr_width-2]))]),
(rd_timing, [ (rd_timing, [
self.bus.dat_o[16:].eq(self.d), self.bus.dat_o[16:].eq(self.d),

2
milkymist/uart/__init__.py
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@ -2,7 +2,7 @@ from migen.fhdl.structure import *
from migen.bank.description import * from migen.bank.description import *
from migen.bank import csrgen from migen.bank import csrgen
class Inst: class UART:
def __init__(self, address, clk_freq, baud=115200): def __init__(self, address, clk_freq, baud=115200):
self._rxtx = rxtx = Register("rxtx", BV(8)) self._rxtx = rxtx = Register("rxtx", BV(8))
divisor = Register("divisor") divisor = Register("divisor")

12
top.py
View File

@ -9,18 +9,18 @@ def get():
MHz = 1000000 MHz = 1000000
clk_freq = 80*MHz clk_freq = 80*MHz
clkfx_sys = clkfx.Inst(50*MHz, clk_freq) clkfx_sys = clkfx.ClkFX(50*MHz, clk_freq)
reset0 = m1reset.Inst() reset0 = m1reset.M1Reset()
cpu0 = lm32.Inst() cpu0 = lm32.LM32()
norflash0 = norflash.Inst(25, 12) norflash0 = norflash.NorFlash(25, 12)
wishbone2csr0 = wishbone2csr.Inst() wishbone2csr0 = wishbone2csr.WB2CSR()
wishbonecon0 = wishbone.InterconnectShared( wishbonecon0 = wishbone.InterconnectShared(
[cpu0.ibus, cpu0.dbus], [cpu0.ibus, cpu0.dbus],
[(0, norflash0.bus), (3, wishbone2csr0.wishbone)], [(0, norflash0.bus), (3, wishbone2csr0.wishbone)],
register=True, register=True,
offset=1) offset=1)
uart0 = uart.Inst(0, clk_freq, baud=115200) uart0 = uart.UART(0, clk_freq, baud=115200)
csrcon0 = csr.Interconnect(wishbone2csr0.csr, [uart0.bank.interface]) csrcon0 = csr.Interconnect(wishbone2csr0.csr, [uart0.bank.interface])
frag = autofragment.from_local() frag = autofragment.from_local()