mibuild: get rid of Platform factory function, cleanup

examples/cordic/cordic_impl.py

@@ -6,7 +6,7 @@ from migen.genlib.cordic import Cordic
 from mibuild.tools import mkdir_noerror
 from mibuild.generic_platform import *
 from mibuild.crg import SimpleCRG
-from mibuild.xilinx.ise import XilinxISEPlatform
+from mibuild.xilinx import XilinxPlatform
 
 class CordicImpl(Module):
 	def __init__(self, name, **kwargs):
@@ -27,7 +27,7 @@ class CordicImpl(Module):
 	def build(self):
 		self.platform.build(self, build_name=self.name)
 
-class Platform(XilinxISEPlatform):
+class Platform(XilinxPlatform):
 	_io = [
 		("clk", 0, Pins("AB13")),
 		("rst", 0, Pins("V5")),
@@ -38,7 +38,7 @@ class Platform(XilinxISEPlatform):
 		),
 	]
 	def __init__(self):
-		XilinxISEPlatform.__init__(self, "xc6slx45-fgg484-2", self._io,
+		XilinxPlatform.__init__(self, "xc6slx45-fgg484-2", self._io,
 			lambda p: SimpleCRG(p, "clk", "rst"))
 
 if __name__ == "__main__":

mibuild/generic_platform.py

@@ -285,3 +285,6 @@ class GenericPlatform:
 		argdict = dict((k, autotype(v)) for k, v in zip(*[iter(arg)]*2))
 		kwargs.update(argdict)
 		self.build(*args, **kwargs)
+
+	def create_programmer(self):
+		raise NotImplementedError

mibuild/platforms/apf27.py

@@ -1,6 +1,6 @@
 from mibuild.generic_platform import *
 from mibuild.crg import SimpleCRG
-from mibuild.xilinx.ise import XilinxISEPlatform
+from mibuild.xilinx import XilinxPlatform
 
 _ios = [
 	("clk0", 0, Pins("N9"), IOStandard("LVCMOS18")),
@@ -141,11 +141,12 @@ _connectors = [
 		"None")  # 116 USBH2_CLK USB_HOST2 +2V5 PA0
 ]
 
-class Platform(XilinxISEPlatform):
+class Platform(XilinxPlatform):
 	default_clk_name = "clk0"
 	default_clk_period = 10
+
 	def __init__(self):
-		XilinxISEPlatform.__init__(self, "xc3s200a-ft256-4", _ios,
+		XilinxPlatform.__init__(self, "xc3s200a-ft256-4", _ios,
 			lambda p: SimpleCRG(p, "clk0", None), _connectors)
 
 	def do_finalize(self, fragment):

mibuild/platforms/apf51.py

@@ -1,6 +1,6 @@
 from mibuild.generic_platform import *
 from mibuild.crg import SimpleCRG
-from mibuild.xilinx.ise import XilinxISEPlatform
+from mibuild.xilinx import XilinxPlatform
 
 _ios = [
 	("clk3", 0, Pins("N8"), IOStandard("LVCMOS33")),
@@ -168,11 +168,12 @@ _connectors = [
 			"None")  # 140 FPGA_BANK3_POWER
 ]
 
-class Platform(XilinxISEPlatform):
+class Platform(XilinxPlatform):
 	default_clk_name = "clk3"
 	default_clk_period = 10.526
+
 	def __init__(self):
-		XilinxISEPlatform.__init__(self, "xc6slx9-2csg225", _ios,
+		XilinxPlatform.__init__(self, "xc6slx9-2csg225", _ios,
 			lambda p: SimpleCRG(p, "clk3", None), _connectors)
 
 	def do_finalize(self, fragment):
@@ -180,4 +181,3 @@ class Platform(XilinxISEPlatform):
 			self.add_period_constraint(self.lookup_request("clk3"), 10.526)
 		except ConstraintError:
 			pass
-

mibuild/platforms/de0nano.py

@@ -94,6 +94,7 @@ _io = [
 class Platform(AlteraQuartusPlatform):
 	default_clk_name = "clk50"
 	default_clk_period = 20
+
 	def __init__(self):
 		AlteraQuartusPlatform.__init__(self, "EP4CE22F17C6", _io,
 			lambda p: SimpleCRG(p, "clk50", None))

mibuild/platforms/kc705.py

@@ -1,9 +1,8 @@
 from mibuild.generic_platform import *
 from mibuild.crg import SimpleCRG
+from mibuild.xilinx import XilinxPlatform, XC3SProg, VivadoProgrammer
+from mibuild.xilinx.ise import XilinxISEToolchain
 from mibuild.xilinx.common import CRG_DS
-from mibuild.xilinx.ise import XilinxISEPlatform
-from mibuild.xilinx.vivado import XilinxVivadoPlatform
-from mibuild.xilinx.programmer import XC3SProg, VivadoProgrammer
 
 _io = [
 	("user_led", 0, Pins("AB8"), IOStandard("LVCMOS15")),
@@ -378,47 +377,41 @@ _connectors = [
 	)
 ]
 
-def Platform(*args, toolchain="vivado", programmer="xc3sprog", **kwargs):
-	if toolchain == "ise":
-		xilinx_platform = XilinxISEPlatform
-	elif toolchain == "vivado":
-		xilinx_platform = XilinxVivadoPlatform
-	else:
-		raise ValueError
+class Platform(XilinxPlatform):
+	identifier = 0x4B37
+	default_clk_name = "clk156"
+	default_clk_period = 6.4
 
-	class RealPlatform(xilinx_platform):
-		identifier = 0x4B37
-		default_clk_name = "clk156"
-		default_clk_period = 6.4
-		bitgen_opt = "-g LCK_cycle:6 -g Binary:Yes -w -g ConfigRate:12 -g SPI_buswidth:4"
+	def __init__(self, toolchain="vivado", programmer="xc3sprog"):
+		XilinxPlatform.__init__(self, "xc7k325t-ffg900-2", _io, 
+			default_crg_factory=lambda p: CRG_DS(p, "clk156", "cpu_reset"),
+			connectors=_connectors,
+			toolchain=toolchain)
+		self.bitgen_opt = "-g LCK_cycle:6 -g Binary:Yes -w -g ConfigRate:12 -g SPI_buswidth:4"
+		self.programmer = programmer
 
-		def __init__(self, crg_factory=lambda p: CRG_DS(p, "clk156", "cpu_reset")):
-			xilinx_platform.__init__(self, "xc7k325t-ffg900-2", _io, crg_factory, _connectors)
+	def create_programmer(self):
+		if self.programmer == "xc3sprog":
+			return XC3SProg("jtaghs1_fast", "bscan_spi_kc705.bit")
+		elif self.programmer == "vivado":
+			return VivadoProgrammer()
+		else:
+			raise ValueError("{} programmer is not supported".format(programmer))
 
-		def create_programmer(self):
-			if programmer == "xc3sprog":
-				return XC3SProg("jtaghs1_fast", "bscan_spi_kc705.bit")
-			elif programmer == "vivado":
-				return VivadoProgrammer()
-			else:
-				raise ValueError("{} programmer is not supported".format(programmer))
-
-		def do_finalize(self, fragment):
-			try:
-				self.add_period_constraint(self.lookup_request("clk156").p, 6.4)
-			except ConstraintError:
-				pass
-			try:
-				self.add_period_constraint(self.lookup_request("clk200").p, 5.0)
-			except ConstraintError:
-				pass
-			try:
-				self.add_period_constraint(self.lookup_request("eth_clocks").rx, 8.0)
-			except ConstraintError:
-				pass
-			if isinstance(self, XilinxISEPlatform):
-				self.add_platform_command("CONFIG DCI_CASCADE = \"33 32 34\";")
-			else:
-				self.add_platform_command("set_property DCI_CASCADE {{32 34}} [get_iobanks 33]")
-
-	return RealPlatform(*args, **kwargs)
+	def do_finalize(self, fragment):
+		try:
+			self.add_period_constraint(self.lookup_request("clk156").p, 6.4)
+		except ConstraintError:
+			pass
+		try:
+			self.add_period_constraint(self.lookup_request("clk200").p, 5.0)
+		except ConstraintError:
+			pass
+		try:
+			self.add_period_constraint(self.lookup_request("eth_clocks").rx, 8.0)
+		except ConstraintError:
+			pass
+		if isinstance(self.toolchain, XilinxISEToolchain):
+			self.add_platform_command("CONFIG DCI_CASCADE = \"33 32 34\";")
+		else:
+			self.add_platform_command("set_property DCI_CASCADE {{32 34}} [get_iobanks 33]")

mibuild/platforms/lx9_microboard.py

@@ -1,6 +1,6 @@
 from mibuild.generic_platform import *
 from mibuild.crg import SimpleCRG
-from mibuild.xilinx.ise import XilinxISEPlatform
+from mibuild.xilinx import XilinxPlatform
 
 _io = [
 		("user_btn", 0, Pins("V4"), IOStandard("LVCMOS33"),
@@ -102,19 +102,20 @@ _io = [
 		]
 
 
-class Platform(XilinxISEPlatform):
+class Platform(XilinxPlatform):
 	default_clk_name = "clk_y3"
 	default_clk_period = 10
-	bitgen_opt = "-g LCK_cycle:6 -g Binary:Yes -w -g SPI_buswidth:4"
-	ise_commands = """
-promgen -w -spi -c FF -p mcs -o {build_name}.mcs -u 0 {build_name}.bit
-"""
+	
 	def __init__(self):
-		XilinxISEPlatform.__init__(self, "xc6slx9-2csg324", _io,
+		XilinxPlatform.__init__(self, "xc6slx9-2csg324", _io,
 				lambda p: SimpleCRG(p, "clk_y3", "user_btn"))
 		self.add_platform_command("""
 CONFIG VCCAUX = "3.3";
 """)
+		self.bitgen_opt = "-g LCK_cycle:6 -g Binary:Yes -w -g SPI_buswidth:4"
+		self.ise_commands = """
+promgen -w -spi -c FF -p mcs -o {build_name}.mcs -u 0 {build_name}.bit
+"""
 
 	def do_finalize(self, fragment):
 		try:
@@ -130,5 +131,5 @@ CONFIG VCCAUX = "3.3";
 TIMESPEC "TS{phy_tx_clk}_io" = FROM "GRP{phy_tx_clk}" TO "PADS" 10 ns;
 TIMESPEC "TS{phy_rx_clk}_io" = FROM "PADS" TO "GRP{phy_rx_clk}" 10 ns;
 """, phy_rx_clk=eth_clocks.rx, phy_tx_clk=eth_clocks.tx)
-		except ContraintError:
+		except ConstraintError:
 			pass

mibuild/platforms/m1.py

@@ -1,6 +1,6 @@
 from mibuild.generic_platform import *
 from mibuild.crg import SimpleCRG
-from mibuild.xilinx.ise import XilinxISEPlatform
+from mibuild.xilinx import XilinxPlatform
 from mibuild.xilinx.programmer import UrJTAG
 
 _io = [
@@ -118,12 +118,13 @@ _io = [
 	)
 ]
 
-class Platform(XilinxISEPlatform):
+class Platform(XilinxPlatform):
 	identifier = 0x4D31
 	default_clk_name = "clk50"
 	default_clk_period = 20
+
 	def __init__(self):
-		XilinxISEPlatform.__init__(self, "xc6slx45-fgg484-2", _io,
+		XilinxPlatform.__init__(self, "xc6slx45-fgg484-2", _io,
 			lambda p: SimpleCRG(p, "clk50", None))
 
 	def create_programmer(self):

mibuild/platforms/mixxeo.py

@@ -1,6 +1,6 @@
 from mibuild.generic_platform import *
 from mibuild.crg import SimpleCRG
-from mibuild.xilinx.ise import XilinxISEPlatform
+from mibuild.xilinx import XilinxPlatform
 from mibuild.xilinx.programmer import UrJTAG
 
 _io = [
@@ -154,12 +154,13 @@ _io = [
 	),
 ]
 
-class Platform(XilinxISEPlatform):
+class Platform(XilinxPlatform):
 	identifier = 0x4D58
 	default_clk_name = "clk50"
 	default_clk_period = 20
+
 	def __init__(self):
-		XilinxISEPlatform.__init__(self, "xc6slx45-fgg484-2", _io,
+		XilinxPlatform.__init__(self, "xc6slx45-fgg484-2", _io,
 			lambda p: SimpleCRG(p, "clk50", None))
 		self.add_platform_command("CONFIG VCCAUX=\"3.3\";\n")
 

mibuild/platforms/ml605.py

@@ -1,6 +1,6 @@
 from mibuild.generic_platform import *
 from mibuild.xilinx.common import CRG_DS
-from mibuild.xilinx.ise import XilinxISEPlatform
+from mibuild.xilinx import XilinxPlatform
 
 _io = [
 	# System clock (Differential 200MHz)
@@ -51,11 +51,12 @@ _io = [
 	)
 ]
 
-class Platform(XilinxISEPlatform):
+class Platform(XilinxPlatform):
 	default_clk_name = "clk200"
 	default_clk_period = 5
+
 	def __init__(self):
-		XilinxISEPlatform.__init__(self, "xc6vlx240t-ff1156-1", _io,
+		XilinxPlatform.__init__(self, "xc6vlx240t-ff1156-1", _io,
 			lambda p: CRG_DS(p, "clk200", "user_btn"))
 
 	def do_finalize(self, fragment):

mibuild/platforms/papilio_pro.py

@@ -1,6 +1,6 @@
 from mibuild.generic_platform import *
 from mibuild.crg import SimpleCRG
-from mibuild.xilinx.ise import XilinxISEPlatform
+from mibuild.xilinx import XilinxPlatform
 from mibuild.xilinx.programmer import XC3SProg
 
 _io = [
@@ -49,12 +49,13 @@ _connectors = [
 	("C", "P114 P115 P116 P117 P118 P119 P120 P121 P123 P124 P126 P127 P131 P132 P133 P134")
 ]
 
-class Platform(XilinxISEPlatform):
+class Platform(XilinxPlatform):
 	identifier = 0x5050
 	default_clk_name = "clk32"
 	default_clk_period = 31.25
+
 	def __init__(self):
-		XilinxISEPlatform.__init__(self, "xc6slx9-tqg144-2", _io,
+		XilinxPlatform.__init__(self, "xc6slx9-tqg144-2", _io,
 			lambda p: SimpleCRG(p, "clk32", None), _connectors)
 
 	def create_programmer(self):

mibuild/platforms/pipistrello.py

@@ -1,6 +1,6 @@
 from mibuild.generic_platform import *
 from mibuild.crg import SimpleCRG
-from mibuild.xilinx.ise import XilinxISEPlatform
+from mibuild.xilinx import XilinxPlatform
 from mibuild.xilinx.programmer import XC3SProg
 
 _io = [
@@ -124,13 +124,13 @@ _connectors = [
 	("C", "F17 F16 E16 G16 F15 G14 F14 H14 H13 J13 G13 H12 K14 K13 K12 L12"),
 ]
 
-class Platform(XilinxISEPlatform):
+class Platform(XilinxPlatform):
 	identifier = 0x5049
 	default_clk_name = "clk50"
 	default_clk_period = 20
 
 	def __init__(self):
-		XilinxISEPlatform.__init__(self, "xc6slx45-csg324-2", _io,
+		XilinxPlatform.__init__(self, "xc6slx45-csg324-2", _io,
 			lambda p: SimpleCRG(p, "clk50", None), _connectors)
 
 	def create_programmer(self):

mibuild/platforms/rhino.py

@@ -1,6 +1,6 @@
 from mibuild.generic_platform import *
 from mibuild.xilinx.common import CRG_DS
-from mibuild.xilinx.ise import XilinxISEPlatform
+from mibuild.xilinx import XilinxPlatform
 
 _io = [
 	("user_led", 0, Pins("Y3")),
@@ -133,11 +133,12 @@ _io = [
 	)
 ]
 
-class Platform(XilinxISEPlatform):
+class Platform(XilinxPlatform):
 	default_clk_name = "clk100"
 	default_clk_period = 10
+
 	def __init__(self):
-		XilinxISEPlatform.__init__(self, "xc6slx150t-fgg676-3", _io,
+		XilinxPlatform.__init__(self, "xc6slx150t-fgg676-3", _io,
 			lambda p: CRG_DS(p, "clk100", "gpio"))
 
 	def do_finalize(self, fragment):

mibuild/platforms/roach.py

@@ -1,5 +1,5 @@
 from mibuild.generic_platform import *
-from mibuild.xilinx.ise import XilinxISEPlatform
+from mibuild.xilinx import XilinxPlatform
 
 _io = [
 	("epb", 0,
@@ -28,6 +28,6 @@ _io = [
 	),
 ]
 
-class Platform(XilinxISEPlatform):
+class Platform(XilinxPlatform):
 	def __init__(self):
-		XilinxISEPlatform.__init__(self, "xc5vsx95t-ff1136-1", _io)
+		XilinxPlatform.__init__(self, "xc5vsx95t-ff1136-1", _io)

mibuild/platforms/sim.py

@@ -36,6 +36,7 @@ class Platform(VerilatorPlatform):
 	is_sim = True
 	default_clk_name = "sys_clk"
 	default_clk_period = 1000 # on modern computers simulate at ~ 1MHz
+
 	def __init__(self):
 		VerilatorPlatform.__init__(self, "SIM", _io)
 

mibuild/platforms/usrp_b100.py

@@ -1,6 +1,6 @@
 from mibuild.generic_platform import *
 from mibuild.xilinx.common import CRG_DS
-from mibuild.xilinx.ise import XilinxISEPlatform
+from mibuild.xilinx import XilinxPlatform
 
 _io = [
 		("clk64", 0,
@@ -113,13 +113,14 @@ _io = [
 ]
 
 
-class Platform(XilinxISEPlatform):
+class Platform(XilinxPlatform):
 	default_clk_name = "clk64"
 	default_clk_period = 15.625
-	bitgen_opt = "-g LCK_cycle:6 -g Binary:Yes -w -g UnusedPin:PullUp"
+
 	def __init__(self):
-		XilinxISEPlatform.__init__(self, "xc3s1400a-ft256-4", _io,
+		XilinxPlatform.__init__(self, "xc3s1400a-ft256-4", _io,
 			lambda p: CRG_DS(p, "clk64", "reset_n", rst_invert=True))
+		self.bitgen_opt = "-g LCK_cycle:6 -g Binary:Yes -w -g UnusedPin:PullUp"
 
 	def do_finalize(self, fragment):
 		try:

mibuild/platforms/zedboard.py

@@ -1,6 +1,6 @@
 from mibuild.generic_platform import *
 from mibuild.crg import SimpleCRG
-from mibuild.xilinx.ise import XilinxISEPlatform
+from mibuild.xilinx import XilinxPlatform
 
 # Bank 34 and 35 voltage depend on J18 jumper setting
 _io = [
@@ -137,11 +137,12 @@ _io = [
 ]
 
 
-class Platform(XilinxISEPlatform):
+class Platform(XilinxPlatform):
 	default_clk_name = "clk100"
 	default_clk_period = 10
+
 	def __init__(self):
-		XilinxISEPlatform.__init__(self, "xc7z020-clg484-1", _io,
+		XilinxPlatform.__init__(self, "xc7z020-clg484-1", _io,
 			lambda p: SimpleCRG(p, "clk100", None))
 
 	def do_finalize(self, fragment):

mibuild/platforms/ztex_115d.py

@@ -1,6 +1,6 @@
 from mibuild.generic_platform import *
 from mibuild.crg import SimpleCRG
-from mibuild.xilinx.ise import XilinxISEPlatform
+from mibuild.xilinx import XilinxPlatform
 
 _io = [
 		("clk_fx", 0, Pins("L22"), IOStandard("LVCMOS33")),
@@ -81,11 +81,12 @@ _io = [
 
 ]
 
-class Platform(XilinxISEPlatform):
+class Platform(XilinxPlatform):
+	default_clk_name = "clk_if"
+	default_clk_period = 20
+
 	def __init__(self):
-		default_clk_name = "clk_if"
-		default_clk_period = 20
-		XilinxISEPlatform.__init__(self, "xc6slx150-3csg484", _io,
+		XilinxPlatform.__init__(self, "xc6slx150-3csg484", _io,
 				lambda p: SimpleCRG(p, "clk_if", "rst"))
 		self.add_platform_command("""
 CONFIG VCCAUX = "2.5";
@@ -108,5 +109,5 @@ TIMESPEC "TSclk_if" = PERIOD "GRPclk_if" 20 ns HIGH 50%;
 TIMESPEC "TSclk_fx2if" = FROM "GRPclk_fx" TO "GRPclk_if" 3 ns DATAPATHONLY;
 TIMESPEC "TSclk_if2fx" = FROM "GRPclk_if" TO "GRPclk_fx" 3 ns DATAPATHONLY;
 """, clk_if=clk_if, clk_fx=clk_fx)
-		except ContraintError:
+		except ConstraintError:
 			pass

mibuild/xilinx/__init__.py

@@ -0,0 +1,2 @@
+from mibuild.xilinx.platform import XilinxPlatform
+from mibuild.xilinx.programmer import UrJTAG, XC3SProg, FpgaProg, VivadoProgrammer

mibuild/xilinx/common.py

@@ -4,9 +4,6 @@ from distutils.version import StrictVersion
 from migen.fhdl.std import *
 from migen.fhdl.specials import SynthesisDirective
 from migen.genlib.cdc import *
-from migen.genlib.resetsync import AsyncResetSynchronizer
-from migen.genlib.io import *
-from mibuild.generic_platform import GenericPlatform
 from mibuild import tools
 
 def settings(path, ver=None, sub=None):
@@ -30,7 +27,7 @@ def settings(path, ver=None, sub=None):
 		if os.path.exists(settings):
 			return settings
 
-	raise ValueError("no settings file found")
+	raise OSError("no settings file found")
 
 class CRG_DS(Module):
 	def __init__(self, platform, clk_name, rst_name, rst_invert=False):
@@ -100,20 +97,3 @@ class XilinxDifferentialOutput:
 	@staticmethod
 	def lower(dr):
 		return XilinxDifferentialOutputImpl(dr.i, dr.o_p, dr.o_n)
-
-class XilinxGenericPlatform(GenericPlatform):
-	bitstream_ext = ".bit"
-
-	def get_verilog(self, *args, special_overrides=dict(), **kwargs):
-		so = {
-			NoRetiming:					XilinxNoRetiming,
-			MultiReg:					XilinxMultiReg,
-			AsyncResetSynchronizer:		XilinxAsyncResetSynchronizer,
-			DifferentialInput:			XilinxDifferentialInput,
-			DifferentialOutput:			XilinxDifferentialOutput,
-		}
-		so.update(special_overrides)
-		return GenericPlatform.get_verilog(self, *args, special_overrides=so, **kwargs)
-
-	def get_edif(self, fragment, **kwargs):
-		return GenericPlatform.get_edif(self, fragment, "UNISIMS", "Xilinx", self.device, **kwargs)

mibuild/xilinx/ise.py

@@ -120,50 +120,51 @@ bitgen {bitgen_opt} {build_name}.ncd {build_name}.bit
 	if r != 0:
 		raise OSError("Subprocess failed")
 
-class XilinxISEPlatform(common.XilinxGenericPlatform):
-	xst_opt = """-ifmt MIXED
+class XilinxISEToolchain:
+	def __init__(self):
+		self.xst_opt = """-ifmt MIXED
 -opt_mode SPEED
 -register_balancing yes"""
-	map_opt = "-ol high -w"
-	par_opt = "-ol high -w"
-	ngdbuild_opt = ""
-	bitgen_opt = "-g LCK_cycle:6 -g Binary:Yes -w"
-	ise_commands = ""
+		self.map_opt = "-ol high -w"
+		self.par_opt = "-ol high -w"
+		self.ngdbuild_opt = ""
+		self.bitgen_opt = "-g LCK_cycle:6 -g Binary:Yes -w"
+		self.ise_commands = ""
 
-	def build(self, fragment, build_dir="build", build_name="top",
+	def build(self, platform, fragment, build_dir="build", build_name="top",
 			ise_path="/opt/Xilinx", source=True, run=True, mode="xst"):
 		tools.mkdir_noerror(build_dir)
 		os.chdir(build_dir)
 
 		if not isinstance(fragment, _Fragment):
 			fragment = fragment.get_fragment()
-		self.finalize(fragment)
+		platform.finalize(fragment)
 
 		ngdbuild_opt = self.ngdbuild_opt
 
 		vns = None
 
 		if mode == "xst" or mode == "yosys":
-			v_src, vns = self.get_verilog(fragment)
-			named_sc, named_pc = self.resolve_signals(vns)
+			v_src, vns = platform.get_verilog(fragment)
+			named_sc, named_pc = platform.resolve_signals(vns)
 			v_file = build_name + ".v"
 			tools.write_to_file(v_file, v_src)
-			sources = self.sources + [(v_file, "verilog")]
+			sources = platform.sources + [(v_file, "verilog")]
 			if mode == "xst":
-				_build_xst_files(self.device, sources, self.verilog_include_paths, build_name, self.xst_opt)
+				_build_xst_files(platform.device, sources, platform.verilog_include_paths, build_name, self.xst_opt)
 				isemode = "xst"
 			else:
-				_run_yosys(self.device, sources, self.verilog_include_paths, build_name)
+				_run_yosys(platform.device, sources, platform.verilog_include_paths, build_name)
 				isemode = "edif"
-				ngdbuild_opt += "-p " + self.device
+				ngdbuild_opt += "-p " + platform.device
 
 		if mode == "mist":
 			from mist import synthesize
-			synthesize(fragment, self.constraint_manager.get_io_signals())
+			synthesize(fragment, platform.constraint_manager.get_io_signals())
 
 		if mode == "edif" or mode == "mist":
-			e_src, vns = self.get_edif(fragment)
-			named_sc, named_pc = self.resolve_signals(vns)
+			e_src, vns = platform.get_edif(fragment)
+			named_sc, named_pc = platform.resolve_signals(vns)
 			e_file = build_name + ".edif"
 			tools.write_to_file(e_file, e_src)
 			isemode = "edif"
@@ -178,6 +179,6 @@ class XilinxISEPlatform(common.XilinxGenericPlatform):
 
 		return vns
 
-	def add_period_constraint(self, clk, period):
-		self.add_platform_command("""NET "{clk}" TNM_NET = "GRP{clk}";
+	def add_period_constraint(self, platform, clk, period):
+		platform.add_platform_command("""NET "{clk}" TNM_NET = "GRP{clk}";
 TIMESPEC "TS{clk}" = PERIOD "GRP{clk}" """+str(period)+""" ns HIGH 50%;""", clk=clk)

mibuild/xilinx/platform.py

@@ -0,0 +1,39 @@
+from migen.genlib.cdc import *
+from migen.genlib.resetsync import AsyncResetSynchronizer
+from migen.genlib.io import *
+
+from mibuild.generic_platform import GenericPlatform
+from mibuild.xilinx import common, vivado, ise
+
+class XilinxPlatform(GenericPlatform):
+	bitstream_ext = ".bit"
+
+	def __init__(self, *args, toolchain="ise", **kwargs):
+		GenericPlatform.__init__(self, *args, **kwargs)
+		if toolchain == "ise":
+			self.toolchain = ise.XilinxISEToolchain()
+		elif toolchain == "vivado":
+			self.toolchain = vivado.XilinxVivadoToolchain()
+		else:
+			raise ValueError("Unknown toolchain")
+
+	def get_verilog(self, *args, special_overrides=dict(), **kwargs):
+		so = {
+			NoRetiming:					common.XilinxNoRetiming,
+			MultiReg:					common.XilinxMultiReg,
+			AsyncResetSynchronizer:		common.XilinxAsyncResetSynchronizer,
+			DifferentialInput:			common.XilinxDifferentialInput,
+			DifferentialOutput:			common.XilinxDifferentialOutput,
+		}
+		so.update(special_overrides)
+		return GenericPlatform.get_verilog(self, *args, special_overrides=so, **kwargs)
+
+	def get_edif(self, fragment, **kwargs):
+		return GenericPlatform.get_edif(self, fragment, "UNISIMS", "Xilinx", self.device, **kwargs)
+
+
+	def build(self, *args, **kwargs):
+		return self.toolchain.build(self, *args, **kwargs)
+
+	def add_period_constraint(self, clk, period):
+		self.toolchain.add_period_constraint(self, clk, period)

mibuild/xilinx/vivado.py

@@ -93,26 +93,25 @@ def _run_vivado(build_name, vivado_path, source, ver=None):
 	if r != 0:
 		raise OSError("Subprocess failed")
 
-class XilinxVivadoPlatform(common.XilinxGenericPlatform):
-	def __init__(self, *args, **kwargs):
-		common.XilinxGenericPlatform.__init__(self, *args, **kwargs)
+class XilinxVivadoToolchain:
+	def __init__(self):
 		self.bitstream_commands = []
 		self.additional_commands = []
 
-	def build(self, fragment, build_dir="build", build_name="top",
+	def build(self, platform, fragment, build_dir="build", build_name="top",
 			vivado_path="/opt/Xilinx/Vivado", source=True, run=True):
 		tools.mkdir_noerror(build_dir)
 		os.chdir(build_dir)
 
 		if not isinstance(fragment, _Fragment):
 			fragment = fragment.get_fragment()
-		self.finalize(fragment)
-		v_src, vns = self.get_verilog(fragment)
-		named_sc, named_pc = self.resolve_signals(vns)
+		platform.finalize(fragment)
+		v_src, vns = platform.get_verilog(fragment)
+		named_sc, named_pc = platform.resolve_signals(vns)
 		v_file = build_name + ".v"
 		tools.write_to_file(v_file, v_src)
-		sources = self.sources + [(v_file, "verilog")]
-		_build_files(self.device, sources, self.verilog_include_paths, build_name,
+		sources = platform.sources + [(v_file, "verilog")]
+		_build_files(platform.device, sources, platform.verilog_include_paths, build_name,
 			self.bitstream_commands, self.additional_commands)
 		tools.write_to_file(build_name + ".xdc", _build_xdc(named_sc, named_pc))
 		if run:
@@ -122,6 +121,6 @@ class XilinxVivadoPlatform(common.XilinxGenericPlatform):
 
 		return vns
 
-	def add_period_constraint(self, clk, period):
-		self.add_platform_command("""create_clock -name {clk} -period """ +\
+	def add_period_constraint(self, platform, clk, period):
+		platform.add_platform_command("""create_clock -name {clk} -period """ + \
 			str(period) + """ [get_ports {clk}]""", clk=clk)