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crg: apply constraint to IO pins, not internal signals

This commit is contained in:
Sebastien Bourdeauducq 2013-04-08 20:28:11 +02:00
parent 8cf7c96a53
commit 715d332c3d
2 changed files with 6 additions and 4 deletions
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8
mibuild/crg.py
View File

@ -3,9 +3,11 @@ from migen.fhdl.module import Module
class SimpleCRG(Module): class SimpleCRG(Module):
def __init__(self, platform, clk_name, rst_name, rst_invert=False): def __init__(self, platform, clk_name, rst_name, rst_invert=False):
self._clk = platform.request(clk_name)
self._rst = platform.request(rst_name)
self.clock_domains.cd_sys = ClockDomain() self.clock_domains.cd_sys = ClockDomain()
self.comb += self.cd_sys.clk.eq(platform.request(clk_name)) self.comb += self.cd_sys.clk.eq(self._clk)
if rst_invert: if rst_invert:
self.comb += self.cd_sys.rst.eq(~platform.request(rst_name)) self.comb += self.cd_sys.rst.eq(~self._rst)
else: else:
self.comb += self.cd_sys.rst.eq(platform.request(rst_name)) self.comb += self.cd_sys.rst.eq(self._rst)

2
mibuild/xilinx_ise.py
View File

@ -17,7 +17,7 @@ TIMESPEC "TSclk" = PERIOD "GRPclk" """+str(period)+""" ns HIGH 50%;""", clk=clk)
class CRG_SE(SimpleCRG): class CRG_SE(SimpleCRG):
def __init__(self, platform, clk_name, rst_name, period, rst_invert=False): def __init__(self, platform, clk_name, rst_name, period, rst_invert=False):
SimpleCRG.__init__(self, platform, clk_name, rst_name, rst_invert) SimpleCRG.__init__(self, platform, clk_name, rst_name, rst_invert)
_add_period_constraint(platform, self.cd_sys.clk, period) _add_period_constraint(platform, self._clk, period)
class CRG_DS(Module): class CRG_DS(Module):
def __init__(self, platform, clk_name, rst_name, period, rst_invert=False): def __init__(self, platform, clk_name, rst_name, period, rst_invert=False):