crg: use new platform.request
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@ -4,9 +4,8 @@ from migen.fhdl.module import Module
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class SimpleCRG(Module):
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def __init__(self, platform, clk_name, rst_name, rst_invert=False):
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self.clock_domains.cd_sys = ClockDomain()
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platform.request(clk_name, None, self.cd_sys.clk)
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self.comb += self.cd_sys.clk.eq(platform.request(clk_name))
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if rst_invert:
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rst_n = platform.request(rst_name)
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self.comb += self.cd_sys.rst.eq(~rst_n)
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self.comb += self.cd_sys.rst.eq(~platform.request(rst_name))
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else:
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platform.request(rst_name, None, self.cd_sys.rst)
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self.comb += self.cd_sys.rst.eq(platform.request(rst_name))
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@ -24,10 +24,9 @@ class CRG_DS(Module):
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self.clock_domains.cd_sys = ClockDomain()
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self._clk = platform.request(clk_name)
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if rst_invert:
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rst_n = platform.request(rst_name)
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self.comb += self.cd_sys.rst.eq(~rst_n)
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self.comb += self.cd_sys.rst.eq(~platform.request(rst_name))
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else:
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platform.request(rst_name, None, self.cd_sys.rst)
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self.comb += self.cd_sys.rst.eq(platform.request(rst_name))
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_add_period_constraint(platform, self._clk.p, period)
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self.specials += Instance("IBUFGDS",
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Instance.Input("I", self._clk.p),
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