Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

global: pep8 (W262)

This commit is contained in:
Florent Kermarrec 2015-04-13 17:02:59 +02:00
parent f3c010c1d5
commit 71d0f6ab2a
2 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
misoclib/com/spi/test/spi_master_tb.py
View File

@ -83,4 +83,4 @@ class TB(Module):
print("{:08x}".format(selfp.spi_master._miso.status))
if __name__ == "__main__":
run_simulation(TB(), ncycles=1000, vcd_name="my.vcd", keep_files=True)
run_simulation(TB(), ncycles=1000, vcd_name="my.vcd", keep_files=True)

2
misoclib/cpu/lm32/__init__.py
View File

@ -60,4 +60,4 @@ class LM32(Module):
"lm32_shifter.v", "lm32_multiplier.v", "lm32_mc_arithmetic.v",
"lm32_interrupt.v", "lm32_ram.v", "lm32_dp_ram.v", "lm32_icache.v",
"lm32_dcache.v", "lm32_debug.v", "lm32_itlb.v", "lm32_dtlb.v")
platform.add_verilog_include_path(os.path.join("extcores", "lm32"))
platform.add_verilog_include_path(os.path.join("extcores", "lm32"))