global: pep8 (W262)
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@ -83,4 +83,4 @@ class TB(Module):
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print("{:08x}".format(selfp.spi_master._miso.status))
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print("{:08x}".format(selfp.spi_master._miso.status))
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if __name__ == "__main__":
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if __name__ == "__main__":
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run_simulation(TB(), ncycles=1000, vcd_name="my.vcd", keep_files=True)
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run_simulation(TB(), ncycles=1000, vcd_name="my.vcd", keep_files=True)
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@ -60,4 +60,4 @@ class LM32(Module):
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"lm32_shifter.v", "lm32_multiplier.v", "lm32_mc_arithmetic.v",
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"lm32_shifter.v", "lm32_multiplier.v", "lm32_mc_arithmetic.v",
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"lm32_interrupt.v", "lm32_ram.v", "lm32_dp_ram.v", "lm32_icache.v",
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"lm32_interrupt.v", "lm32_ram.v", "lm32_dp_ram.v", "lm32_icache.v",
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"lm32_dcache.v", "lm32_debug.v", "lm32_itlb.v", "lm32_dtlb.v")
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"lm32_dcache.v", "lm32_debug.v", "lm32_itlb.v", "lm32_dtlb.v")
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platform.add_verilog_include_path(os.path.join("extcores", "lm32"))
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platform.add_verilog_include_path(os.path.join("extcores", "lm32"))
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