crt0-or1k: clean up indentation
This commit is contained in:
Sebastien Bourdeauducq
parent
b437dc3185
commit
73d3b8487c
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@ -21,338 +21,338 @@
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#define EXCEPTION_STACK_SIZE (128+128)
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#define HANDLE_EXCEPTION ; \
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l.addi r1, r1, -EXCEPTION_STACK_SIZE ; \
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l.sw 0x1c(r1), r9 ; \
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l.jal _exception_handler ; \
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l.nop ; \
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l.lwz r9, 0x1c(r1) ; \
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l.addi r1, r1, EXCEPTION_STACK_SIZE ; \
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l.rfe ; \
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l.nop
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#define HANDLE_EXCEPTION ; \
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l.addi r1, r1, -EXCEPTION_STACK_SIZE ; \
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l.sw 0x1c(r1), r9 ; \
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l.jal _exception_handler ; \
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l.nop ; \
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l.lwz r9, 0x1c(r1) ; \
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l.addi r1, r1, EXCEPTION_STACK_SIZE ; \
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l.rfe ; \
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l.nop
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.section .text, "ax", @progbits
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.global _start
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_start:
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_reset_handler:
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l.movhi r0, 0
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l.movhi r1, 0
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l.movhi r2, 0
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l.movhi r3, 0
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l.movhi r4, 0
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l.movhi r5, 0
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l.movhi r6, 0
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l.movhi r7, 0
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l.movhi r8, 0
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l.movhi r9, 0
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l.movhi r10, 0
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l.movhi r11, 0
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l.movhi r12, 0
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l.movhi r13, 0
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l.movhi r14, 0
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l.movhi r15, 0
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l.movhi r16, 0
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l.movhi r17, 0
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l.movhi r18, 0
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l.movhi r19, 0
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l.movhi r20, 0
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l.movhi r21, 0
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l.movhi r22, 0
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l.movhi r23, 0
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l.movhi r24, 0
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l.movhi r25, 0
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l.movhi r26, 0
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l.movhi r27, 0
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l.movhi r28, 0
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l.movhi r29, 0
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l.movhi r30, 0
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l.movhi r31, 0
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l.movhi r0, 0
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l.movhi r1, 0
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l.movhi r2, 0
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l.movhi r3, 0
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l.movhi r4, 0
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l.movhi r5, 0
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l.movhi r6, 0
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l.movhi r7, 0
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l.movhi r8, 0
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l.movhi r9, 0
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l.movhi r10, 0
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l.movhi r11, 0
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l.movhi r12, 0
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l.movhi r13, 0
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l.movhi r14, 0
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l.movhi r15, 0
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l.movhi r16, 0
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l.movhi r17, 0
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l.movhi r18, 0
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l.movhi r19, 0
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l.movhi r20, 0
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l.movhi r21, 0
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l.movhi r22, 0
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l.movhi r23, 0
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l.movhi r24, 0
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l.movhi r25, 0
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l.movhi r26, 0
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l.movhi r27, 0
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l.movhi r28, 0
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l.movhi r29, 0
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l.movhi r30, 0
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l.movhi r31, 0
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l.ori r21, r0, SPR_SR_SM
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l.mtspr r0, r21, SPR_SR
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l.movhi r21, hi(_reset_handler)
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l.ori r21, r21, lo(_reset_handler)
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l.mtspr r0, r21, SPR_EVBAR
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/* enable caches */
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l.jal _cache_init
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l.nop
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l.j _crt0
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l.nop
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l.ori r21, r0, SPR_SR_SM
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l.mtspr r0, r21, SPR_SR
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l.movhi r21, hi(_reset_handler)
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l.ori r21, r21, lo(_reset_handler)
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l.mtspr r0, r21, SPR_EVBAR
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/* enable caches */
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l.jal _cache_init
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l.nop
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l.j _crt0
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l.nop
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/* bus error */
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.org 0x200
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HANDLE_EXCEPTION
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/* bus error */
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.org 0x200
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HANDLE_EXCEPTION
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/* data page fault */
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.org 0x300
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HANDLE_EXCEPTION
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/* data page fault */
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.org 0x300
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HANDLE_EXCEPTION
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/* instruction page fault */
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.org 0x400
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HANDLE_EXCEPTION
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/* instruction page fault */
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.org 0x400
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HANDLE_EXCEPTION
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/* tick timer */
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.org 0x500
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HANDLE_EXCEPTION
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/* tick timer */
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.org 0x500
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HANDLE_EXCEPTION
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/* alignment */
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.org 0x600
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HANDLE_EXCEPTION
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/* alignment */
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.org 0x600
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HANDLE_EXCEPTION
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/* illegal instruction */
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.org 0x700
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HANDLE_EXCEPTION
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/* illegal instruction */
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.org 0x700
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HANDLE_EXCEPTION
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/* external interrupt */
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.org 0x800
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HANDLE_EXCEPTION
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/* external interrupt */
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.org 0x800
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HANDLE_EXCEPTION
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/* D-TLB miss */
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.org 0x900
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HANDLE_EXCEPTION
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/* D-TLB miss */
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.org 0x900
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HANDLE_EXCEPTION
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/* I-TLB miss */
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.org 0xa00
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HANDLE_EXCEPTION
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/* I-TLB miss */
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.org 0xa00
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HANDLE_EXCEPTION
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/* range */
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.org 0xb00
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HANDLE_EXCEPTION
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/* range */
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.org 0xb00
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HANDLE_EXCEPTION
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/* system call */
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.org 0xc00
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HANDLE_EXCEPTION
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/* system call */
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.org 0xc00
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HANDLE_EXCEPTION
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/* floating point */
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.org 0xd00
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HANDLE_EXCEPTION
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/* floating point */
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.org 0xd00
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HANDLE_EXCEPTION
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/* trap */
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.org 0xe00
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HANDLE_EXCEPTION
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/* trap */
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.org 0xe00
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HANDLE_EXCEPTION
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/* reserved */
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.org 0xf00
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HANDLE_EXCEPTION
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/* reserved */
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.org 0xf00
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HANDLE_EXCEPTION
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.org 0x1000
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.org 0x1000
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_crt0:
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/* Setup stack and global pointer */
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l.movhi r1, hi(_fstack)
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l.ori r1, r1, lo(_fstack)
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/* Setup stack and global pointer */
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l.movhi r1, hi(_fstack)
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l.ori r1, r1, lo(_fstack)
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/*
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l.movhi r16, hi(_gp)
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l.ori r16, gp, lo(_gp)
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l.movhi r16, hi(_gp)
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l.ori r16, gp, lo(_gp)
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*/
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/* Clear BSS */
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l.movhi r21, hi(_fbss)
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l.ori r21, r21, lo(_fbss)
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l.movhi r3, hi(_ebss)
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l.ori r3, r3, lo(_ebss)
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/* Clear BSS */
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l.movhi r21, hi(_fbss)
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l.ori r21, r21, lo(_fbss)
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l.movhi r3, hi(_ebss)
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l.ori r3, r3, lo(_ebss)
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.clearBSS:
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l.sfeq r21, r3
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l.bf .callMain
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l.nop
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l.sw 0(r21), r0
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l.addi r21, r21, 4
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l.j .clearBSS
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l.nop
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l.sfeq r21, r3
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l.bf .callMain
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l.nop
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l.sw 0(r21), r0
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l.addi r21, r21, 4
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l.j .clearBSS
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l.nop
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.callMain:
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l.j main
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l.nop
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l.j main
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l.nop
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_exception_handler:
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l.sw 0x00(r1), r2
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l.sw 0x04(r1), r3
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l.sw 0x08(r1), r4
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l.sw 0x0c(r1), r5
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l.sw 0x10(r1), r6
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l.sw 0x14(r1), r7
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l.sw 0x18(r1), r8
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l.sw 0x20(r1), r10
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l.sw 0x24(r1), r11
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l.sw 0x28(r1), r12
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l.sw 0x2c(r1), r13
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l.sw 0x30(r1), r14
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l.sw 0x34(r1), r15
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l.sw 0x38(r1), r16
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l.sw 0x3c(r1), r17
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l.sw 0x40(r1), r18
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l.sw 0x44(r1), r19
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l.sw 0x48(r1), r20
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l.sw 0x4c(r1), r21
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l.sw 0x50(r1), r22
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l.sw 0x54(r1), r23
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l.sw 0x58(r1), r24
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l.sw 0x5c(r1), r25
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l.sw 0x60(r1), r26
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l.sw 0x64(r1), r27
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l.sw 0x68(r1), r28
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l.sw 0x6c(r1), r29
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l.sw 0x70(r1), r30
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l.sw 0x74(r1), r31
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l.sw 0x00(r1), r2
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l.sw 0x04(r1), r3
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l.sw 0x08(r1), r4
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l.sw 0x0c(r1), r5
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l.sw 0x10(r1), r6
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l.sw 0x14(r1), r7
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l.sw 0x18(r1), r8
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l.sw 0x20(r1), r10
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l.sw 0x24(r1), r11
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l.sw 0x28(r1), r12
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l.sw 0x2c(r1), r13
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l.sw 0x30(r1), r14
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l.sw 0x34(r1), r15
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l.sw 0x38(r1), r16
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l.sw 0x3c(r1), r17
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l.sw 0x40(r1), r18
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l.sw 0x44(r1), r19
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l.sw 0x48(r1), r20
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l.sw 0x4c(r1), r21
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l.sw 0x50(r1), r22
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l.sw 0x54(r1), r23
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l.sw 0x58(r1), r24
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l.sw 0x5c(r1), r25
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l.sw 0x60(r1), r26
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l.sw 0x64(r1), r27
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l.sw 0x68(r1), r28
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l.sw 0x6c(r1), r29
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l.sw 0x70(r1), r30
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l.sw 0x74(r1), r31
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/* Save return address */
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l.or r14, r0, r9
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/* send stack pointer as argument */
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l.or r4, r0, r1
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/* Call exception handler with the link address as argument */
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l.jal exception_handler
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l.or r3, r0, r14
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/* Save return address */
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l.or r14, r0, r9
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/* send stack pointer as argument */
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l.or r4, r0, r1
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/* Call exception handler with the link address as argument */
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l.jal exception_handler
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l.or r3, r0, r14
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/* Load return address */
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l.or r9, r0, r14
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/* Restore state */
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l.lwz r2, 0x00(r1)
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l.lwz r3, 0x04(r1)
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l.lwz r4, 0x08(r1)
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l.lwz r5, 0x0c(r1)
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l.lwz r6, 0x10(r1)
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l.lwz r7, 0x14(r1)
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l.lwz r8, 0x18(r1)
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l.lwz r10, 0x20(r1)
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l.lwz r11, 0x24(r1)
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l.lwz r12, 0x28(r1)
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l.lwz r13, 0x2c(r1)
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l.lwz r14, 0x30(r1)
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l.lwz r15, 0x34(r1)
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l.lwz r16, 0x38(r1)
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l.lwz r17, 0x3c(r1)
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l.lwz r18, 0x40(r1)
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l.lwz r19, 0x44(r1)
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l.lwz r20, 0x48(r1)
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l.lwz r21, 0x4c(r1)
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l.lwz r22, 0x50(r1)
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l.lwz r23, 0x54(r1)
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l.lwz r24, 0x58(r1)
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l.lwz r25, 0x5c(r1)
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l.lwz r26, 0x60(r1)
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l.lwz r27, 0x64(r1)
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l.lwz r28, 0x68(r1)
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l.lwz r29, 0x6c(r1)
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l.lwz r30, 0x70(r1)
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l.lwz r31, 0x74(r1)
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l.jr r9
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l.nop
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/* Load return address */
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l.or r9, r0, r14
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/* Restore state */
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l.lwz r2, 0x00(r1)
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l.lwz r3, 0x04(r1)
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l.lwz r4, 0x08(r1)
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l.lwz r5, 0x0c(r1)
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l.lwz r6, 0x10(r1)
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l.lwz r7, 0x14(r1)
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l.lwz r8, 0x18(r1)
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l.lwz r10, 0x20(r1)
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l.lwz r11, 0x24(r1)
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l.lwz r12, 0x28(r1)
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l.lwz r13, 0x2c(r1)
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l.lwz r14, 0x30(r1)
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l.lwz r15, 0x34(r1)
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l.lwz r16, 0x38(r1)
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l.lwz r17, 0x3c(r1)
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l.lwz r18, 0x40(r1)
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l.lwz r19, 0x44(r1)
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l.lwz r20, 0x48(r1)
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l.lwz r21, 0x4c(r1)
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l.lwz r22, 0x50(r1)
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l.lwz r23, 0x54(r1)
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l.lwz r24, 0x58(r1)
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l.lwz r25, 0x5c(r1)
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l.lwz r26, 0x60(r1)
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l.lwz r27, 0x64(r1)
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l.lwz r28, 0x68(r1)
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l.lwz r29, 0x6c(r1)
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l.lwz r30, 0x70(r1)
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l.lwz r31, 0x74(r1)
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l.jr r9
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l.nop
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_cache_init:
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/*
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This function is to be used ONLY during reset, before main() is called.
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TODO: Perhaps break into individual enable instruction/data cache
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sections functions, and provide disable functions, also, all
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callable from C
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*/
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/*
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This function is to be used ONLY during reset, before main() is called.
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TODO: Perhaps break into individual enable instruction/data cache
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sections functions, and provide disable functions, also, all
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callable from C
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*/
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/* Instruction cache enable */
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/* Check if IC present and skip enabling otherwise */
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/* Instruction cache enable */
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/* Check if IC present and skip enabling otherwise */
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#if 1
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.L6:
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l.mfspr r3,r0,SPR_UPR
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l.andi r7,r3,SPR_UPR_ICP
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l.sfeq r7,r0
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l.bf .L8
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l.nop
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l.mfspr r3,r0,SPR_UPR
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l.andi r7,r3,SPR_UPR_ICP
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l.sfeq r7,r0
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l.bf .L8
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l.nop
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/* Disable IC */
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l.mfspr r6,r0,SPR_SR
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l.addi r5,r0,-1
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l.xori r5,r5,SPR_SR_ICE
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l.and r5,r6,r5
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l.mtspr r0,r5,SPR_SR
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/* Disable IC */
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l.mfspr r6,r0,SPR_SR
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l.addi r5,r0,-1
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l.xori r5,r5,SPR_SR_ICE
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l.and r5,r6,r5
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l.mtspr r0,r5,SPR_SR
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/* Establish cache block size
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If BS=0, 16;
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If BS=1, 32;
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r14 contain block size
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*/
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l.mfspr r3,r0,SPR_ICCFGR
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l.andi r7,r3,SPR_ICCFGR_CBS
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l.srli r8,r7,7
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l.ori r4,r0,16
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l.sll r14,r4,r8
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/* Establish cache block size
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If BS=0, 16;
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If BS=1, 32;
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r14 contain block size
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*/
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l.mfspr r3,r0,SPR_ICCFGR
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||||
l.andi r7,r3,SPR_ICCFGR_CBS
|
||||
l.srli r8,r7,7
|
||||
l.ori r4,r0,16
|
||||
l.sll r14,r4,r8
|
||||
|
||||
/* Establish number of cache sets
|
||||
r10 contains number of cache sets
|
||||
r8 contains log(# of cache sets)
|
||||
*/
|
||||
l.andi r7,r3,SPR_ICCFGR_NCS
|
||||
l.srli r8,r7,3
|
||||
l.ori r4,r0,1
|
||||
l.sll r10,r4,r8
|
||||
/* Establish number of cache sets
|
||||
r10 contains number of cache sets
|
||||
r8 contains log(# of cache sets)
|
||||
*/
|
||||
l.andi r7,r3,SPR_ICCFGR_NCS
|
||||
l.srli r8,r7,3
|
||||
l.ori r4,r0,1
|
||||
l.sll r10,r4,r8
|
||||
|
||||
/* Invalidate IC */
|
||||
l.addi r6,r0,0
|
||||
l.sll r5,r14,r8
|
||||
/* Invalidate IC */
|
||||
l.addi r6,r0,0
|
||||
l.sll r5,r14,r8
|
||||
|
||||
.L7: l.mtspr r0,r6,SPR_ICBIR
|
||||
l.sfne r6,r5
|
||||
l.bf .L7
|
||||
l.add r6,r6,r14
|
||||
.L7: l.mtspr r0,r6,SPR_ICBIR
|
||||
l.sfne r6,r5
|
||||
l.bf .L7
|
||||
l.add r6,r6,r14
|
||||
|
||||
/* Enable IC */
|
||||
l.mfspr r6,r0,SPR_SR
|
||||
l.ori r6,r6,SPR_SR_ICE
|
||||
l.mtspr r0,r6,SPR_SR
|
||||
l.nop
|
||||
l.nop
|
||||
l.nop
|
||||
l.nop
|
||||
l.nop
|
||||
l.nop
|
||||
l.nop
|
||||
l.nop
|
||||
/* Data cache enable */
|
||||
/* Check if DC present and skip enabling otherwise */
|
||||
/* Enable IC */
|
||||
l.mfspr r6,r0,SPR_SR
|
||||
l.ori r6,r6,SPR_SR_ICE
|
||||
l.mtspr r0,r6,SPR_SR
|
||||
l.nop
|
||||
l.nop
|
||||
l.nop
|
||||
l.nop
|
||||
l.nop
|
||||
l.nop
|
||||
l.nop
|
||||
l.nop
|
||||
/* Data cache enable */
|
||||
/* Check if DC present and skip enabling otherwise */
|
||||
#endif
|
||||
.L8:
|
||||
#if 1
|
||||
l.mfspr r3,r0,SPR_UPR
|
||||
l.andi r7,r3,SPR_UPR_DCP
|
||||
l.sfeq r7,r0
|
||||
l.bf .L10
|
||||
l.nop
|
||||
/* Disable DC */
|
||||
l.mfspr r6,r0,SPR_SR
|
||||
l.addi r5,r0,-1
|
||||
l.xori r5,r5,SPR_SR_DCE
|
||||
l.and r5,r6,r5
|
||||
l.mtspr r0,r5,SPR_SR
|
||||
/* Establish cache block size
|
||||
If BS=0, 16;
|
||||
If BS=1, 32;
|
||||
r14 contain block size
|
||||
*/
|
||||
l.mfspr r3,r0,SPR_DCCFGR
|
||||
l.andi r7,r3,SPR_DCCFGR_CBS
|
||||
l.srli r8,r7,7
|
||||
l.ori r4,r0,16
|
||||
l.sll r14,r4,r8
|
||||
/* Establish number of cache sets
|
||||
r10 contains number of cache sets
|
||||
r8 contains log(# of cache sets)
|
||||
*/
|
||||
l.andi r7,r3,SPR_DCCFGR_NCS
|
||||
l.srli r8,r7,3
|
||||
l.ori r4,r0,1
|
||||
l.sll r10,r4,r8
|
||||
/* Invalidate DC */
|
||||
l.addi r6,r0,0
|
||||
l.sll r5,r14,r8
|
||||
l.mfspr r3,r0,SPR_UPR
|
||||
l.andi r7,r3,SPR_UPR_DCP
|
||||
l.sfeq r7,r0
|
||||
l.bf .L10
|
||||
l.nop
|
||||
/* Disable DC */
|
||||
l.mfspr r6,r0,SPR_SR
|
||||
l.addi r5,r0,-1
|
||||
l.xori r5,r5,SPR_SR_DCE
|
||||
l.and r5,r6,r5
|
||||
l.mtspr r0,r5,SPR_SR
|
||||
/* Establish cache block size
|
||||
If BS=0, 16;
|
||||
If BS=1, 32;
|
||||
r14 contain block size
|
||||
*/
|
||||
l.mfspr r3,r0,SPR_DCCFGR
|
||||
l.andi r7,r3,SPR_DCCFGR_CBS
|
||||
l.srli r8,r7,7
|
||||
l.ori r4,r0,16
|
||||
l.sll r14,r4,r8
|
||||
/* Establish number of cache sets
|
||||
r10 contains number of cache sets
|
||||
r8 contains log(# of cache sets)
|
||||
*/
|
||||
l.andi r7,r3,SPR_DCCFGR_NCS
|
||||
l.srli r8,r7,3
|
||||
l.ori r4,r0,1
|
||||
l.sll r10,r4,r8
|
||||
/* Invalidate DC */
|
||||
l.addi r6,r0,0
|
||||
l.sll r5,r14,r8
|
||||
|
||||
.L9:
|
||||
l.mtspr r0,r6,SPR_DCBIR
|
||||
l.sfne r6,r5
|
||||
l.bf .L9
|
||||
l.add r6,r6,r14
|
||||
/* Enable DC */
|
||||
l.mfspr r6,r0,SPR_SR
|
||||
l.ori r6,r6,SPR_SR_DCE
|
||||
l.mtspr r0,r6,SPR_SR
|
||||
l.mtspr r0,r6,SPR_DCBIR
|
||||
l.sfne r6,r5
|
||||
l.bf .L9
|
||||
l.add r6,r6,r14
|
||||
/* Enable DC */
|
||||
l.mfspr r6,r0,SPR_SR
|
||||
l.ori r6,r6,SPR_SR_DCE
|
||||
l.mtspr r0,r6,SPR_SR
|
||||
#endif
|
||||
.L10:
|
||||
/* Return */
|
||||
l.jr r9
|
||||
l.nop
|
||||
/* Return */
|
||||
l.jr r9
|
||||
l.nop
|
||||
|
|
|
|||
Loading…
Reference in New Issue