Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

la: fix intput_buffer clocking when clk_domain is not "sys"

This commit is contained in:
Florent Kermarrec 2015-02-19 11:41:54 +01:00
parent 37e463da9a
commit 741ecca5b4
1 changed files with 7 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
litescope/frontend/la.py
View File

@ -34,9 +34,13 @@ class LiteScopeLA(Module, AutoCSR):
sink = self.sink sink = self.sink
# insert Buffer on sink (optional, can be used to improve timings) # insert Buffer on sink (optional, can be used to improve timings)
if self.with_input_buffer: if self.with_input_buffer:
self.submodules.buffer = Buffer(self.sink.description) input_buffer = Buffer(self.sink.description)
self.comb += Record.connect(sink, self.buffer.d) if self.clk_domain is not "sys":
sink = self.buffer.q self.submodules += RenameClockDomains(input_buffer, clk_domain)
else:
self.submodules += input_buffer
self.comb += Record.connect(sink, intput_buffer.d)
sink = intput_buffer.q
# clock domain crossing (optional, required when capture_clk is not sys_clk) # clock domain crossing (optional, required when capture_clk is not sys_clk)
# XXX : sys_clk must be faster than capture_clk, add Converter on data to remove this limitation # XXX : sys_clk must be faster than capture_clk, add Converter on data to remove this limitation