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test/test_targets: add arty_symbiflow 

Signed-off-by: Mariusz Glebocki <mglebocki@antmicro.com>
This commit is contained in:
Mariusz Glebocki 2020-06-01 13:58:44 +02:00
parent ae121aacdf
commit 7434376c07
1 changed files with 16 additions and 9 deletions
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25
test/test_targets.py
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@ -73,6 +73,13 @@ class TestTargets(unittest.TestCase):
]) ])
self.assertEqual(errors, 0) self.assertEqual(errors, 0)
def test_arty_symbiflow(self):
from litex.boards.targets.arty_symbiflow import BaseSoC
errors = build_test([
BaseSoC(**test_kwargs)
])
self.assertEqual(errors, 0)
# Kintex-7 # Kintex-7
def test_genesys2(self): def test_genesys2(self):
from litex.boards.targets.genesys2 import BaseSoC from litex.boards.targets.genesys2 import BaseSoC
@ -112,21 +119,21 @@ class TestTargets(unittest.TestCase):
def test_simple(self): def test_simple(self):
platforms = [] platforms = []
# Xilinx # Xilinx
platforms += ["minispartan6"] # Spartan6 platforms += ["minispartan6"] # Spartan6
platforms += ["arty", "netv2", "nexys4ddr", "nexys_video"] # Artix7 platforms += ["arty", "netv2", "nexys4ddr", "nexys_video", "arty_symbiflow"] # Artix7
platforms += ["kc705", "genesys2"] # Kintex7 platforms += ["kc705", "genesys2"] # Kintex7
platforms += ["kcu105"] # Kintex Ultrascale platforms += ["kcu105"] # Kintex Ultrascale
# Altera/Intel # Altera/Intel
platforms += ["de0nano"] # Cyclone4 platforms += ["de0nano"] # Cyclone4
# Lattice # Lattice
platforms += ["tinyfpga_bx"] # iCE40 platforms += ["tinyfpga_bx"] # iCE40
platforms += ["machxo3"] # MachXO3 platforms += ["machxo3"] # MachXO3
platforms += ["versa_ecp5", "ulx3s"] # ECP5 platforms += ["versa_ecp5", "ulx3s"] # ECP5
# Microsemi # Microsemi
platforms += ["avalanche"] # PolarFire platforms += ["avalanche"] # PolarFire
for p in platforms: for p in platforms:
with self.subTest(platform=p): with self.subTest(platform=p):