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integration/soc/add_pcie: add with_msi parameter to allow disabling MSI when not required. 

When just doing a PCIe to Wishbone Bridge (PCIeBone), DMAs and MSI are not required, with_msi
will allow disabling MSI when set to False.
This commit is contained in:
Florent Kermarrec 2021-02-19 11:35:49 +01:00
parent d4edc132c1
commit 7513460572
1 changed files with 12 additions and 9 deletions
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21
litex/soc/integration/soc.py
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@ -1574,7 +1574,7 @@ class LiteXSoC(SoC):
self.sata_phy.crg.cd_sata_rx.clk) self.sata_phy.crg.cd_sata_rx.clk)
# Add PCIe ------------------------------------------------------------------------------------- # Add PCIe -------------------------------------------------------------------------------------
def add_pcie(self, name="pcie", phy=None, ndmas=0, max_pending_requests=8): def add_pcie(self, name="pcie", phy=None, ndmas=0, max_pending_requests=8, with_msi=True):
assert self.csr.data_width == 32 assert self.csr.data_width == 32
assert not hasattr(self, f"{name}_endpoint") assert not hasattr(self, f"{name}_endpoint")
@ -1593,14 +1593,16 @@ class LiteXSoC(SoC):
setattr(self.submodules, f"{name}_mmap", mmap) setattr(self.submodules, f"{name}_mmap", mmap)
# MSI # MSI
msi = LitePCIeMSI() if with_msi:
setattr(self.submodules, f"{name}_msi", msi) msi = LitePCIeMSI()
self.add_csr(f"{name}_msi") setattr(self.submodules, f"{name}_msi", msi)
self.comb += msi.source.connect(phy.msi) self.add_csr(f"{name}_msi")
self.msis = {} self.comb += msi.source.connect(phy.msi)
self.msis = {}
# DMAs # DMAs
for i in range(ndmas): for i in range(ndmas):
assert with_msi
dma = LitePCIeDMA(phy, endpoint, dma = LitePCIeDMA(phy, endpoint,
with_buffering = True, buffering_depth=1024, with_buffering = True, buffering_depth=1024,
with_loopback = True) with_loopback = True)
@ -1611,9 +1613,10 @@ class LiteXSoC(SoC):
self.add_constant("DMA_CHANNELS", ndmas) self.add_constant("DMA_CHANNELS", ndmas)
# Map/Connect IRQs # Map/Connect IRQs
for i, (k, v) in enumerate(sorted(self.msis.items())): if with_msi:
self.comb += msi.irqs[i].eq(v) for i, (k, v) in enumerate(sorted(self.msis.items())):
self.add_constant(k + "_INTERRUPT", i) self.comb += msi.irqs[i].eq(v)
self.add_constant(k + "_INTERRUPT", i)
# Timing constraints # Timing constraints
self.platform.add_false_path_constraints(self.crg.cd_sys.clk, phy.cd_pcie.clk) self.platform.add_false_path_constraints(self.crg.cd_sys.clk, phy.cd_pcie.clk)