integration/soc/add_pcie: add with_msi parameter to allow disabling MSI when not required.

When just doing a PCIe to Wishbone Bridge (PCIeBone), DMAs and MSI are not required, with_msi
will allow disabling MSI when set to False.

litex/soc/integration/soc.py

@@ -1574,7 +1574,7 @@ class LiteXSoC(SoC):
             self.sata_phy.crg.cd_sata_rx.clk)
 
     # Add PCIe -------------------------------------------------------------------------------------
-    def add_pcie(self, name="pcie", phy=None, ndmas=0, max_pending_requests=8):
+    def add_pcie(self, name="pcie", phy=None, ndmas=0, max_pending_requests=8, with_msi=True):
         assert self.csr.data_width == 32
         assert not hasattr(self, f"{name}_endpoint")
 
@@ -1593,6 +1593,7 @@ class LiteXSoC(SoC):
         setattr(self.submodules, f"{name}_mmap", mmap)
 
         # MSI
+        if with_msi:
             msi = LitePCIeMSI()
             setattr(self.submodules, f"{name}_msi", msi)
             self.add_csr(f"{name}_msi")
@@ -1601,6 +1602,7 @@ class LiteXSoC(SoC):
 
         # DMAs
         for i in range(ndmas):
+            assert with_msi
             dma = LitePCIeDMA(phy, endpoint,
                 with_buffering = True, buffering_depth=1024,
                 with_loopback  = True)
@@ -1611,6 +1613,7 @@ class LiteXSoC(SoC):
         self.add_constant("DMA_CHANNELS", ndmas)
 
         # Map/Connect IRQs
+        if with_msi:
             for i, (k, v) in enumerate(sorted(self.msis.items())):
                 self.comb += msi.irqs[i].eq(v)
                 self.add_constant(k + "_INTERRUPT", i)