commit
7556d551b4
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@ -155,15 +155,16 @@ def generate_dts(d, initrd_start=None, initrd_size=None, polling=False):
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if cpu_name == "vexriscv smp-linux":
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dts += """
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intc0: interrupt-controller@{plic_base:x} {{
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compatible = "sifive,plic-1.0.0", "sifive,fu540-c000-plic";
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compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
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reg = <0x{plic_base:x} 0x400000>;
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-controller;
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interrupts-extended = <
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{cpu_mapping}>;
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riscv,ndev = <32>;
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}};
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""".format(
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""".format(
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plic_base =d["memories"]["plic"]["base"],
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cpu_mapping =("\n" + " "*20).join(["&L{} 11 &L{} 9".format(cpu, cpu) for cpu in cpus]))
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@ -182,7 +183,6 @@ def generate_dts(d, initrd_start=None, initrd_size=None, polling=False):
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aliases["serial0"] = "liteuart0"
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dts += """
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liteuart0: serial@{uart_csr_base:x} {{
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device_type = "serial";
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compatible = "litex,liteuart";
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reg = <0x{uart_csr_base:x} 0x100>;
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{uart_interrupt}
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@ -267,15 +267,14 @@ def generate_dts(d, initrd_start=None, initrd_size=None, polling=False):
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dts += """
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mmc0: mmc@{mmc_csr_base:x} {{
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compatible = "litex,mmc";
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reg = <
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0x{sdphy_csr_base:x} 0x100
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0x{sdcore_csr_base:x} 0x100
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0x{sdblock2mem:x} 0x100
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0x{sdmem2block:x} 0x100>;
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reg = <0x{sdphy_csr_base:x} 0x100>,
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<0x{sdcore_csr_base:x} 0x100>,
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<0x{sdblock2mem:x} 0x100>,
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<0x{sdmem2block:x} 0x100>;
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bus-width = <0x04>;
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status = "okay";
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}};
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""".format(
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""".format(
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mmc_csr_base = d["csr_bases"]["sdphy"],
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sdphy_csr_base = d["csr_bases"]["sdphy"],
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sdcore_csr_base = d["csr_bases"]["sdcore"],
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