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Replace __riscv__ macros with __riscv. 

The __riscv__ form is deprecated [1].

[1] - https://github.com/riscv/riscv-toolchain-conventions#cc-preprocessor-definitions
This commit is contained in:
Sergiusz Bazanski 2018-01-21 21:46:25 +00:00
parent 20ed23443b
commit 75e230aae7
4 changed files with 6 additions and 6 deletions
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2
litex/soc/software/bios/main.c
View File

@ -497,7 +497,7 @@ int main(int i, char **c)
printf("\e[1mLM32\e[0m\n"); printf("\e[1mLM32\e[0m\n");
#elif __or1k__ #elif __or1k__
printf("\e[1mOR1K\e[0m\n"); printf("\e[1mOR1K\e[0m\n");
#elif __riscv__ #elif __riscv
printf("\e[1mRISC-V\n"); printf("\e[1mRISC-V\n");
#else #else
printf("\e[1mUnknown\e[0m\n"); printf("\e[1mUnknown\e[0m\n");

2
litex/soc/software/bios/sdram.c
View File

@ -18,7 +18,7 @@ static void cdelay(int i)
__asm__ volatile("nop"); __asm__ volatile("nop");
#elif defined (__or1k__) #elif defined (__or1k__)
__asm__ volatile("l.nop"); __asm__ volatile("l.nop");
#elif defined (__riscv__) #elif defined (__riscv)
__asm__ volatile("nop"); __asm__ volatile("nop");
#else #else
#error Unsupported architecture #error Unsupported architecture

2
litex/soc/software/common.mak
View File

@ -1,7 +1,7 @@
TARGET_PREFIX=$(TRIPLE)- TARGET_PREFIX=$(TRIPLE)-
RM ?= rm -f RM ?= rm -f
PYTHON ?= python3 PYTHON ?= python
ifeq ($(CLANG),1) ifeq ($(CLANG),1)
CC_normal := clang -target $(TRIPLE) -integrated-as CC_normal := clang -target $(TRIPLE) -integrated-as

6
litex/soc/software/libbase/system.c
View File

@ -34,7 +34,7 @@ void flush_cpu_icache(void)
for (i = 0; i < cache_size; i += cache_block_size) for (i = 0; i < cache_size; i += cache_block_size)
mtspr(SPR_ICBIR, i); mtspr(SPR_ICBIR, i);
#elif defined (__riscv__) #elif defined (__riscv)
/* no instruction cache */ /* no instruction cache */
asm volatile("nop"); asm volatile("nop");
#else #else
@ -65,7 +65,7 @@ void flush_cpu_dcache(void)
for (i = 0; i < cache_size; i += cache_block_size) for (i = 0; i < cache_size; i += cache_block_size)
mtspr(SPR_DCBIR, i); mtspr(SPR_DCBIR, i);
#elif defined (__riscv__) #elif defined (__riscv)
/* no data cache */ /* no data cache */
asm volatile("nop"); asm volatile("nop");
#else #else
@ -86,7 +86,7 @@ void flush_l2_cache(void)
__asm__ volatile("lw %0, (%1+0)\n":"=r"(dummy):"r"(addr)); __asm__ volatile("lw %0, (%1+0)\n":"=r"(dummy):"r"(addr));
#elif defined (__or1k__) #elif defined (__or1k__)
__asm__ volatile("l.lwz %0, 0(%1)\n":"=r"(dummy):"r"(addr)); __asm__ volatile("l.lwz %0, 0(%1)\n":"=r"(dummy):"r"(addr));
#elif defined (__riscv__) #elif defined (__riscv)
/* FIXME */ /* FIXME */
asm volatile("nop"); asm volatile("nop");
#else #else