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sdram/phy/simphy: OK with DDR3

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This commit is contained in:
Florent Kermarrec 2015-03-28 01:59:55 +01:00
parent 51ce7cad6f
commit 75ee8a5db9
1 changed files with 1 additions and 3 deletions
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4
misoclib/mem/sdram/phy/simphy.py
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@ -2,10 +2,8 @@
# License: BSD
# SDRAM simulation PHY at DFI level
# Status:
# - tested against software memtest with SDR/DDR/LPDDR/DDR2 with Verilator.
# tested with SDR/DDR/DDR2/LPDDR/DDR3
# TODO:
# - test with DDR3
# - add $display support to Migen and manage timing violations?
from migen.fhdl.std import *