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litex
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fix most imports

This commit is contained in:
Sebastien Bourdeauducq 2015-09-25 18:43:20 +08:00
parent f69674e89c
commit 75ef2f9004
53 changed files with 451 additions and 757 deletions
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2
misoc/cores/framebuffer/__init__.py
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@ -1 +1 @@
from misoc.framebuffer.core import Framebuffer
from misoc.cores.framebuffer.core import Framebuffer

11
misoc/cores/framebuffer/dvi.py
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@ -1,5 +1,8 @@
from functools import reduce
from operator import add
from migen import *
from migen.genlib.misc import optree
control_tokens = [0b1101010100, 0b0010101011, 0b0101010100, 0b1010101011]
@ -18,7 +21,7 @@ class Encoder(Module):
d = Signal(8)
n1d = Signal(max=9)
self.sync += [
n1d.eq(optree("+", [self.d[i] for i in range(8)])),
n1d.eq(reduce(add, [self.d[i] for i in range(8)])),
d.eq(self.d)
]
@ -39,8 +42,8 @@ class Encoder(Module):
n0q_m = Signal(max=9)
n1q_m = Signal(max=9)
self.sync += [
n0q_m.eq(optree("+", [~q_m[i] for i in range(8)])),
n1q_m.eq(optree("+", [q_m[i] for i in range(8)])),
n0q_m.eq(reduce(add, [~q_m[i] for i in range(8)])),
n1q_m.eq(reduce(add, [q_m[i] for i in range(8)])),
q_m_r.eq(q_m)
]

4
misoc/cores/identifier.py
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@ -1,7 +1,9 @@
import subprocess
from migen import *
from migen.bank.description import *
from misoc.interconnect.csr import *
def get_id():
output = subprocess.check_output(["git", "rev-parse", "HEAD"]).decode("ascii")

3
misoc/cores/lasmicon/bankmachine.py
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@ -1,10 +1,9 @@
from migen import *
from migen.genlib.roundrobin import *
from migen.genlib.fsm import FSM, NextState
from migen.genlib.misc import optree
from migen.genlib.fifo import SyncFIFO
from misoc.mem.sdram.core.lasmicon.multiplexer import *
from misoc.cores.lasmicon.multiplexer import *
class _AddressSlicer:

11
misoc/cores/lasmicon/core.py
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@ -1,10 +1,9 @@
from migen import *
from misoc.mem.sdram.phy import dfi
from misoc.mem.sdram.core import lasmibus
from misoc.mem.sdram.core.lasmicon.refresher import *
from misoc.mem.sdram.core.lasmicon.bankmachine import *
from misoc.mem.sdram.core.lasmicon.multiplexer import *
from misoc.interconnect import dfi, lasmi_bus
from misoc.cores.lasmicon.refresher import *
from misoc.cores.lasmicon.bankmachine import *
from misoc.cores.lasmicon.multiplexer import *
class LASMIconSettings:
@ -36,7 +35,7 @@ class LASMIcon(Module):
geom_settings.bankbits,
phy_settings.dfi_databits,
phy_settings.nphases)
self.lasmic = lasmibus.Interface(
self.lasmic = lasmi_bus.Interface(
aw=geom_settings.rowbits + geom_settings.colbits - address_align,
dw=phy_settings.dfi_databits*phy_settings.nphases,
nbanks=2**geom_settings.bankbits,

14
misoc/cores/lasmicon/multiplexer.py
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@ -1,10 +1,12 @@
from functools import reduce
from operator import or_, and_
from migen import *
from migen.genlib.roundrobin import *
from migen.genlib.misc import optree
from migen.genlib.fsm import FSM, NextState
from migen.bank.description import AutoCSR
from misoc.mem.sdram.core.lasmicon.perf import Bandwidth
from misoc.cores.lasmicon.perf import Bandwidth
from misoc.interconnect.csr import AutoCSR
class CommandRequest:
@ -124,8 +126,8 @@ class Multiplexer(Module, AutoCSR):
read_available = Signal()
write_available = Signal()
self.comb += [
read_available.eq(optree("|", [req.stb & req.is_read for req in requests])),
write_available.eq(optree("|", [req.stb & req.is_write for req in requests]))
read_available.eq(reduce(or_, [req.stb & req.is_read for req in requests])),
write_available.eq(reduce(or_, [req.stb & req.is_write for req in requests]))
]
def anti_starvation(timeout):
@ -149,7 +151,7 @@ class Multiplexer(Module, AutoCSR):
# Refresh
self.comb += [bm.refresh_req.eq(refresher.req) for bm in bank_machines]
go_to_refresh = Signal()
self.comb += go_to_refresh.eq(optree("&", [bm.refresh_gnt for bm in bank_machines]))
self.comb += go_to_refresh.eq(reduce(and_, [bm.refresh_gnt for bm in bank_machines]))
# Datapath
all_rddata = [p.rddata for p in dfi.phases]

3
misoc/cores/lasmicon/perf.py
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@ -1,5 +1,6 @@
from migen import *
from migen.bank.description import *
from misoc.interconnect.csr import *
class Bandwidth(Module, AutoCSR):

2
misoc/cores/lasmicon/refresher.py
View File

@ -2,7 +2,7 @@ from migen import *
from migen.genlib.misc import timeline
from migen.genlib.fsm import FSM
from misoc.mem.sdram.core.lasmicon.multiplexer import *
from misoc.cores.lasmicon.multiplexer import *
class Refresher(Module):

22
misoc/cores/liteeth_mini/common.py
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@ -1,16 +1,15 @@
import math
from collections import OrderedDict
from migen import *
from migen.genlib.resetsync import AsyncResetSynchronizer
from migen.genlib.record import *
from migen.genlib.fsm import FSM, NextState
from migen.genlib.misc import chooser, reverse_bytes, FlipFlop, Counter, WaitTimer
from migen.flow.actor import *
from migen.actorlib.structuring import Converter, Pipeline
from migen.actorlib.fifo import SyncFIFO, AsyncFIFO
from migen.actorlib.packet import *
from migen.bank.description import *
from misoc.interconnect.csr import *
# TODO: rewrite without dataflow or implement those
# from migen.flow.actor import *
# from migen.actorlib.structuring import Converter, Pipeline
# from migen.actorlib.fifo import SyncFIFO, AsyncFIFO
# from migen.actorlib.packet import *
class Port:
def connect(self, port):
@ -26,6 +25,7 @@ eth_interpacket_gap = 12
eth_preamble = 0xD555555555555555
buffer_depth = 2**log2_int(eth_mtu, need_pow2=False)
def eth_phy_description(dw):
payload_layout = [
("data", dw),

9
misoc/cores/liteeth_mini/mac/__init__.py
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@ -1,6 +1,9 @@
from misoc.com.liteethmini.common import *
from misoc.com.liteethmini.mac.core import LiteEthMACCore
from misoc.com.liteethmini.mac.frontend.wishbone import LiteEthMACWishboneInterface
from migen import *
from misoc.interconnect.csr import *
from misoc.cores.liteeth_mini.common import *
from misoc.cores.liteeth_mini.mac.core import LiteEthMACCore
from misoc.cores.liteeth_mini.mac.frontend.wishbone import LiteEthMACWishboneInterface
class LiteEthMAC(Module, AutoCSR):

16
misoc/cores/liteeth_mini/mac/core/__init__.py
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@ -1,7 +1,9 @@
from misoc.com.liteethmini.common import *
from misoc.com.liteethmini.mac.core import gap, preamble, crc, padding, last_be
from misoc.com.liteethmini.phy.sim import LiteEthPHYSim
from misoc.com.liteethmini.phy.mii import LiteEthPHYMII
from migen import *
from misoc.interconnect.csr import *
from misoc.cores.liteeth_mini.common import *
from misoc.cores.liteeth_mini.mac.core import gap, preamble, crc, padding, last_be
from misoc.cores.liteeth_mini.phy.mii import LiteEthPHYMII
class LiteEthMACCore(Module, AutoCSR):
@ -24,11 +26,7 @@ class LiteEthMACCore(Module, AutoCSR):
rx_pipeline += [rx_gap_checker]
# Preamble / CRC
if isinstance(phy, LiteEthPHYSim):
# In simulation, avoid CRC/Preamble to enable direct connection
# to the Ethernet tap.
self._preamble_crc = CSRStatus(reset=1)
elif with_preamble_crc:
if with_preamble_crc:
self._preamble_crc = CSRStatus(reset=1)
# Preamble insert/check
preamble_inserter = preamble.LiteEthMACPreambleInserter(phy.dw)

7
misoc/cores/liteeth_mini/mac/core/crc.py
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@ -1,4 +1,4 @@
from misoc.com.liteethmini.common import *
from migen import *
class LiteEthMACCRCEngine(Module):
@ -70,8 +70,8 @@ class LiteEthMACCRCEngine(Module):
self.comb += self.next[i].eq(optree("^", xors))
@DecorateModule(InsertReset)
@DecorateModule(InsertCE)
@ResetInserter()
@CEInserter()
class LiteEthMACCRC32(Module):
"""IEEE 802.3 CRC
@ -224,7 +224,6 @@ class LiteEthMACCRCChecker(Module):
self.submodules += crc
ratio = crc.width//dw
error = Signal()
fifo = InsertReset(SyncFIFO(description, ratio + 1))
self.submodules += fifo

8
misoc/cores/liteeth_mini/mac/core/gap.py
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@ -1,4 +1,10 @@
from misoc.com.liteethmini.common import *
import math
from migen import *
from migen.genlib.fsm import *
from misoc.cores.liteeth_mini.common import eth_phy_description
class LiteEthMACGap(Module):
def __init__(self, dw, ack_on_gap=False):

4
misoc/cores/liteeth_mini/mac/core/last_be.py
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@ -1,4 +1,6 @@
from misoc.com.liteethmini.common import *
from migen import *
from misoc.cores.liteeth_mini.common import eth_phy_description
class LiteEthMACTXLastBE(Module):

6
misoc/cores/liteeth_mini/mac/core/padding.py
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@ -1,4 +1,8 @@
from misoc.com.liteethmini.common import *
from migen import *
from misoc.cores.liteeth_mini.common import eth_phy_description
# TODO: rewrite without Counter
class LiteEthMACPaddingInserter(Module):

6
misoc/cores/liteeth_mini/mac/core/preamble.py
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@ -1,4 +1,8 @@
from misoc.com.liteethmini.common import *
from migen import *
from migen.genlib.fsm import *
from migen.genlib.record import Record
from misoc.cores.liteeth_mini.common import eth_phy_description, eth_preamble
class LiteEthMACPreambleInserter(Module):

8
misoc/cores/liteeth_mini/mac/frontend/sram.py
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@ -1,7 +1,9 @@
from misoc.com.liteethmini.common import *
from misoc import *
from migen.bank.description import *
from migen.bank.eventmanager import *
from misoc.interconnect.csr import *
from misoc.interconnect.csr_eventmanager import *
from misoc.cores.liteeth_mini.common import eth_phy_description
class LiteEthMACSRAMWriter(Module, AutoCSR):

10
misoc/cores/liteeth_mini/mac/frontend/wishbone.py
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@ -1,9 +1,11 @@
from misoc.com.liteethmini.common import *
from misoc.com.liteethmini.mac.frontend import sram
from migen.bus import wishbone
from migen import *
from migen.fhdl.simplify import FullMemoryWE
from misoc.cores.liteeth_mini.common import eth_phy_description
from misoc.cores.liteeth_mini.mac.frontend import sram
from misoc.interconnect import wishbone
from misoc.interconnect.csr import *
class LiteEthMACWishboneInterface(Module, AutoCSR):
def __init__(self, dw, nrxslots=2, ntxslots=2):

2
misoc/cores/liteeth_mini/phy/__init__.py
View File

@ -1,4 +1,4 @@
from misoc.com.liteethmini.common import *
from misoc.cores.liteeth_mini.common import *
def LiteEthPHY(clock_pads, pads, clk_freq=None, **kwargs):

6
misoc/cores/liteeth_mini/phy/mii.py
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@ -1,4 +1,6 @@
from misoc.com.liteethmini.common import *
from migen import *
from misoc.interconnect.csr import *
def converter_description(dw):
@ -44,7 +46,7 @@ class LiteEthPHYMIIRX(Module):
converter = Converter(converter_description(4),
converter_description(8))
converter = InsertReset(converter)
converter = ResetInserter(converter)
self.submodules += converter
self.sync += [

58
misoc/cores/liteeth_mini/phy/sim.py
View File

@ -1,58 +0,0 @@
import os
from misoc.com.liteethmini.common import *
class LiteEthPHYSimCRG(Module, AutoCSR):
def __init__(self):
self._reset = CSRStorage()
# # #
self.clock_domains.cd_eth_rx = ClockDomain()
self.clock_domains.cd_eth_tx = ClockDomain()
self.comb += [
self.cd_eth_rx.clk.eq(ClockSignal()),
self.cd_eth_tx.clk.eq(ClockSignal())
]
reset = self._reset.storage
self.comb += [
self.cd_eth_rx.rst.eq(reset),
self.cd_eth_tx.rst.eq(reset)
]
class LiteEthPHYSim(Module, AutoCSR):
def __init__(self, pads, tap="tap0", ip_address="192.168.0.14"):
self.dw = 8
self.submodules.crg = LiteEthPHYSimCRG()
self.sink = sink = Sink(eth_phy_description(8))
self.source = source = Source(eth_phy_description(8))
self.tap = tap
self.ip_address = ip_address
self.comb += [
pads.source_stb.eq(self.sink.stb),
pads.source_data.eq(self.sink.data),
self.sink.ack.eq(1)
]
self.sync += [
self.source.stb.eq(pads.sink_stb),
self.source.sop.eq(pads.sink_stb & ~self.source.stb),
self.source.data.eq(pads.sink_data),
]
self.comb += [
self.source.eop.eq(~pads.sink_stb & self.source.stb),
]
# XXX avoid use of os.system
os.system("openvpn --mktun --dev {}".format(self.tap))
os.system("ifconfig {} {} up".format(self.tap, self.ip_address))
os.system("mknod /dev/net/{} c 10 200".format(self.tap))
def do_exit(self, *args, **kwargs):
# XXX avoid use of os.system
os.system("rm -f /dev/net/{}".format(self.tap))
os.system("openvpn --rmtun --dev {}".format(self.tap))

21
misoc/cores/minicon/core.py
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@ -1,9 +1,12 @@
from migen import *
from migen.bus import wishbone
from migen.genlib.fsm import FSM, NextState
from migen.genlib.misc import optree, WaitTimer
from functools import reduce
from operator import or_
from misoc.mem.sdram.phy import dfi as dfibus
from migen import *
from migen.genlib.fsm import FSM, NextState
from migen.genlib.misc import WaitTimer
from misoc.interconnect import dfi as dfibus
from misoc.interconnect import wishbone
class _AddressSlicer:
@ -36,8 +39,8 @@ class _AddressSlicer:
return Cat(Replicate(0, self.address_align), address[:split])
@DecorateModule(InsertReset)
@DecorateModule(InsertCE)
@ResetInserter()
@CEInserter()
class _Bank(Module):
def __init__(self, geom_settings):
self.open = Signal()
@ -116,8 +119,8 @@ class Minicon(Module):
self.comb += Case(slicer.bank(bus.adr), cases)
self.comb += [
bank_hit.eq(optree("|", [bank.hit & bank.ce for bank in banks])),
bank_idle.eq(optree("|", [bank.idle & bank.ce for bank in banks])),
bank_hit.eq(reduce(or_, [bank.hit & bank.ce for bank in banks])),
bank_idle.eq(reduce(or_, [bank.idle & bank.ce for bank in banks])),
]
# Timings

3
misoc/cores/nor_flash_16.py
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@ -1,7 +1,8 @@
from migen import *
from migen.bus import wishbone
from migen.genlib.fsm import FSM, NextState
from misoc.interconnect import wishbone
class NorFlash16(Module):
def __init__(self, pads, rd_timing, wr_timing):

6
misoc/cores/sdram_phy/__init__.py
View File

@ -1,3 +1,3 @@
from misoc.cores.sdramphy.gensdrphy import GENSDRPHY
from misoc.cores.sdramphy.s6ddrphy import S6HalfRateDDRPHY, S6QuarterRateDDRPHY
from misoc.cores.sdramphy.k7ddrphy import K7DDRPHY
from misoc.cores.sdram_phy.gensdrphy import GENSDRPHY
from misoc.cores.sdram_phy.s6ddrphy import S6HalfRateDDRPHY, S6QuarterRateDDRPHY
from misoc.cores.sdram_phy.k7ddrphy import K7DDRPHY

7
misoc/cores/sdram_phy/gensdrphy.py
View File

@ -23,10 +23,9 @@
from migen import *
from migen.genlib.record import *
from migen.fhdl.specials import *
from misoc.mem.sdram.phy.dfi import *
from misoc.mem import sdram
from misoc.interconnect.dfi import *
from misoc.cores import sdram_settings
class GENSDRPHY(Module):
@ -35,7 +34,7 @@ class GENSDRPHY(Module):
bankbits = flen(pads.ba)
databits = flen(pads.dq)
self.settings = sdram.PhySettings(
self.settings = sdram_settings.PhySettings(
memtype=module.memtype,
dfi_databits=databits,
nphases=1,

8
misoc/cores/sdram_phy/k7ddrphy.py
View File

@ -1,10 +1,10 @@
# tCK=5ns CL=7 CWL=6
from migen import *
from migen.bank.description import *
from misoc.mem.sdram.phy.dfi import *
from misoc.mem import sdram
from misoc.interconnect.dfi import *
from misoc.interconnect.csr import *
from misoc.cores import sdram_settings
class K7DDRPHY(Module, AutoCSR):
@ -25,7 +25,7 @@ class K7DDRPHY(Module, AutoCSR):
self._wdly_dqs_rst = CSR()
self._wdly_dqs_inc = CSR()
self.settings = sdram.PhySettings(
self.settings = sdram_settings.PhySettings(
memtype=module.memtype,
dfi_databits=2*databits,
nphases=nphases,

17
misoc/cores/sdram_phy/s6ddrphy.py
View File

@ -16,11 +16,14 @@
# Write commands must be sent on phase 1.
#
from functools import reduce
from operator import or_
from migen import *
from migen.genlib.record import *
from misoc.mem.sdram.phy.dfi import *
from misoc.mem import sdram
from misoc.interconnect.dfi import *
from misoc.cores import sdram_settings
class S6HalfRateDDRPHY(Module):
@ -33,7 +36,7 @@ class S6HalfRateDDRPHY(Module):
nphases = 2
if module.memtype == "DDR3":
self.settings = sdram.PhySettings(
self.settings = sdram_settings.PhySettings(
memtype="DDR3",
dfi_databits=2*databits,
nphases=nphases,
@ -47,7 +50,7 @@ class S6HalfRateDDRPHY(Module):
write_latency=2
)
else:
self.settings = sdram.PhySettings(
self.settings = sdram_settings.PhySettings(
memtype=module.memtype,
dfi_databits=2*databits,
nphases=nphases,
@ -361,7 +364,7 @@ class S6HalfRateDDRPHY(Module):
# write
wrdata_en = Signal()
self.comb += wrdata_en.eq(optree("|", [d_dfi[p].wrdata_en for p in range(nphases)]))
self.comb += wrdata_en.eq(reduce(or_, [d_dfi[p].wrdata_en for p in range(nphases)]))
if module.memtype == "DDR3":
r_drive_dq = Signal(self.settings.cwl-1)
@ -383,7 +386,7 @@ class S6HalfRateDDRPHY(Module):
# read
rddata_en = Signal()
self.comb += rddata_en.eq(optree("|", [d_dfi[p].rddata_en for p in range(nphases)]))
self.comb += rddata_en.eq(reduce(or_, [d_dfi[p].rddata_en for p in range(nphases)]))
rddata_sr = Signal(self.settings.read_latency)
sd_sys += rddata_sr.eq(Cat(rddata_sr[1:self.settings.read_latency], rddata_en))
@ -407,7 +410,7 @@ class S6QuarterRateDDRPHY(Module):
databits = flen(pads.dq)
nphases = 4
self.settings = sdram.PhySettings(
self.settings = sdram_settings.PhySettings(
memtype="DDR3",
dfi_databits=2*databits,
nphases=nphases,

5
misoc/cores/sdram_settings.py
View File

@ -2,7 +2,6 @@ from math import ceil
from collections import namedtuple
from migen import *
from misoc.mem import sdram
PhySettingsT = namedtuple("PhySettings", "memtype dfi_databits nphases rdphase wrphase rdcmdphase wrcmdphase cl cwl read_latency write_latency")
@ -31,12 +30,12 @@ class SDRAMModule:
def __init__(self, clk_freq, memtype, geom_settings, timing_settings):
self.clk_freq = clk_freq
self.memtype = memtype
self.geom_settings = sdram.GeomSettings(
self.geom_settings = GeomSettings(
bankbits=log2_int(geom_settings["nbanks"]),
rowbits=log2_int(geom_settings["nrows"]),
colbits=log2_int(geom_settings["ncols"]),
)
self.timing_settings = sdram.TimingSettings(
self.timing_settings = TimingSettings(
tRP=self.ns(timing_settings["tRP"]),
tRCD=self.ns(timing_settings["tRCD"]),
tWR=self.ns(timing_settings["tWR"]),

22
misoc/cores/sdram_tester.py
View File

@ -1,13 +1,16 @@
from functools import reduce
from operator import xor
from migen import *
from migen.genlib.misc import optree
from migen.bank.description import *
from migen.actorlib.spi import *
from misoc.mem.sdram.frontend import dma_lasmi
from misoc.interconnect.csr import *
from misoc.interconnect import dma_lasmi
# TODO: implement or replace DMAControllers in MiSoC
@DecorateModule(InsertReset)
@DecorateModule(InsertCE)
@ResetInserter()
@CEInserter()
class LFSR(Module):
def __init__(self, n_out, n_state=31, taps=[27, 30]):
self.o = Signal(n_out)
@ -18,7 +21,7 @@ class LFSR(Module):
curval = [state[i] for i in range(n_state)]
curval += [0]*(n_out - n_state)
for i in range(n_out):
nv = ~optree("^", [curval[tap] for tap in taps])
nv = ~reduce(xor, [curval[tap] for tap in taps])
curval.insert(0, nv)
curval.pop()
@ -27,10 +30,11 @@ class LFSR(Module):
self.o.eq(Cat(*curval))
]
memtest_magic = 0x361f
class MemtestWriter(Module):
class Writer(Module):
def __init__(self, lasmim):
self._magic = CSRStatus(16)
self._reset = CSR()
@ -68,7 +72,7 @@ class MemtestWriter(Module):
return [self._magic, self._reset, self._shoot] + self._dma.get_csrs()
class MemtestReader(Module):
class Reader(Module):
def __init__(self, lasmim):
self._magic = CSRStatus(16)
self._reset = CSR()

45
misoc/cores/spi_flash.py
View File

@ -1,9 +1,9 @@
from migen import *
from migen.bus.transactions import *
from migen.bus import wishbone
from migen.genlib.misc import timeline
from migen.genlib.record import Record
from migen.bank.description import AutoCSR, CSRStorage, CSRStatus
from misoc.interconnect import wishbone
from misoc.interconnect.csr import AutoCSR, CSRStorage, CSRStatus
_FAST_READ = 0x0b
_DIOFR = 0xbb
@ -142,40 +142,3 @@ class SpiFlash(Module, AutoCSR):
t += dt
self.sync += timeline(bus.cyc & bus.stb & (i == div - 1), tseq)
class SpiFlashTB(Module):
def __init__(self):
self.submodules.master = wishbone.Initiator(self.gen_reads())
self.pads = Record([("cs_n", 1), ("clk", 1), ("dq", 4)])
self.submodules.slave = SpiFlash(self.pads)
self.submodules.tap = wishbone.Tap(self.slave.bus)
self.submodules.intercon = wishbone.InterconnectPointToPoint(
self.master.bus, self.slave.bus)
self.cycle = 0
def gen_reads(self):
for a in range(10):
t = TRead(a)
yield t
print("read {} in {} cycles(s)".format(t.data, t.latency))
def do_simulation(self, selfp):
if selfp.pads.cs_n:
self.cycle = 0
else:
self.cycle += 1
if not selfp.slave.dq.oe:
selfp.slave.dq.i = self.cycle & 0xf
do_simulation.passive = True
if __name__ == "__main__":
from migen.sim.generic import run_simulation
from migen.fhdl import verilog
pads = Record([("cs_n", 1), ("clk", 1), ("dq", 4)])
s = SpiFlash(pads)
print(verilog.convert(s, ios={pads.clk, pads.cs_n, pads.dq, s.bus.adr,
s.bus.dat_r, s.bus.cyc, s.bus.ack, s.bus.stb}))
run_simulation(SpiFlashTB(), vcd_name="spiflash.vcd")

5
misoc/cores/timer.py
View File

@ -1,6 +1,7 @@
from migen import *
from migen.bank.description import *
from migen.bank.eventmanager import *
from misoc.interconnect.csr import *
from misoc.interconnect.csr_eventmanager import *
class Timer(Module, AutoCSR):

2
misoc/cores/uart/__init__.py
View File

@ -1 +1 @@
from misoc.uart.core import UART, RS232PHY
from misoc.cores.uart.core import UART, RS232PHY

10
misoc/cores/uart/core.py
View File

@ -1,15 +1,17 @@
from migen import *
from migen.bank.description import *
from migen.bank.eventmanager import *
from migen.genlib.record import Record
from migen.actorlib.fifo import SyncFIFO, AsyncFIFO
from misoc.interconnect.csr import *
from misoc.interconnect.csr_eventmanager import *
# TODO: from migen.actorlib.fifo import SyncFIFO, AsyncFIFO
# TODO: remove dataflow?
class RS232PHYRX(Module):
def __init__(self, pads, tuning_word):
self.source = Source([("data", 8)])
###
# # #
uart_clk_rxen = Signal()
phase_accumulator_rx = Signal(32)

3
misoc/integration/cpu_interface.py
View File

@ -1,5 +1,6 @@
from migen import *
from migen.bank.description import CSRStatus
from misoc.interconnect.csr import CSRStatus
def get_cpu_mak(cpu_type):

10
misoc/integration/soc_core.py
View File

@ -1,10 +1,9 @@
from operator import itemgetter
from migen import *
from migen.bank import csrgen
from migen.bus import wishbone, csr, wishbone2csr
from misoc import lm32, mor1kx, identifier, timer, uart
from misoc.cores import lm32, mor1kx, identifier, timer, uart
from misoc.interconnect import wishbone, csr_bus, wishbone2csr
def mem_decoder(address, start=26, end=29):
@ -185,10 +184,11 @@ class SoCCore(Module):
# CSR
if self.with_csr:
self.submodules.csrbankarray = csrgen.BankArray(self,
self.submodules.csrbankarray = csr_bus.CSRBankArray(self,
lambda name, memory: self.csr_map[name if memory is None else name + "_" + memory.name_override],
data_width=self.csr_data_width, address_width=self.csr_address_width)
self.submodules.csrcon = csr.Interconnect(self.wishbone2csr.csr, self.csrbankarray.get_buses())
self.submodules.csrcon = csr_bus.Interconnect(
self.wishbone2csr.csr, self.csrbankarray.get_buses())
for name, csrs, mapaddr, rmap in self.csrbankarray.banks:
self.add_csr_region(name, (self.mem_map["csr"] + 0x800*mapaddr) | self.shadow_base, self.csr_data_width, csrs)
for name, memory, mapaddr, mmap in self.csrbankarray.srams:

21
misoc/integration/soc_sdram.py
View File

@ -1,12 +1,15 @@
from migen import *
from migen.bus import wishbone
from migen.genlib.record import *
from misoc.mem.sdram.core.lasmicon import LASMIconSettings
from misoc.mem.sdram.core.minicon import MiniconSettings
from misoc.mem.sdram.frontend import memtest, wishbone2lasmi
from misoc.interconnect import wishbone, wishbone2lasmi
from misoc.interconnect.csr import AutoCSR
from misoc.cores import sdram_tester
from misoc.integration.soc_core import SoCCore
# TODO: cleanup
from misoc.cores.lasmicon.core import LASMIconSettings
from misoc.cores.minicon.core import MiniconSettings
class SDRAMCore(Module, AutoCSR):
def __init__(self, phy, geom_settings, timing_settings, controller_settings, **kwargs):
@ -44,11 +47,11 @@ class SoCSDRAM(SoCCore):
"memtest_w": 10,
"memtest_r": 11
}
csr_map.update(SoC.csr_map)
csr_map.update(SoCCore.csr_map)
def __init__(self, platform, clk_freq, sdram_controller_settings,
**kwargs):
SoC.__init__(self, platform, clk_freq, **kwargs)
SoCCore.__init__(self, platform, clk_freq, **kwargs)
if isinstance(sdram_controller_settings, str):
self.sdram_controller_settings = eval(sdram_controller_settings)
else:
@ -95,8 +98,8 @@ class SoCSDRAM(SoCCore):
self.sdram.controller.multiplexer.add_bandwidth()
if self.sdram_controller_settings.with_memtest:
self.submodules.memtest_w = memtest.MemtestWriter(self.sdram.crossbar.get_master())
self.submodules.memtest_r = memtest.MemtestReader(self.sdram.crossbar.get_master())
self.submodules.memtest_w = sdram_tester.Writer(self.sdram.crossbar.get_master())
self.submodules.memtest_r = sdram_tester.Reader(self.sdram.crossbar.get_master())
if l2_size:
lasmim = self.sdram.crossbar.get_master()
@ -136,4 +139,4 @@ class SoCSDRAM(SoCCore):
# arbitrate wishbone interfaces to the DRAM
self.submodules.wb_sdram_con = wishbone.Arbiter(self._wb_sdram_ifs,
self._wb_sdram)
SoC.do_finalize(self)
SoCCore.do_finalize(self)

16
misoc/interconnect/csr.py
View File

@ -1,11 +1,11 @@
from migen import *
from migen.util.misc import xdir
from migen.fhdl.std import *
from migen.fhdl.tracer import get_obj_var_name
class _CSRBase(HUID):
class _CSRBase(DUID):
def __init__(self, size, name):
HUID.__init__(self)
DUID.__init__(self)
self.name = get_obj_var_name(name)
if self.name is None:
raise ValueError("Cannot extract CSR name from code, need to specify.")
@ -93,16 +93,16 @@ class CSRStorage(_CompoundCSR):
def csrprefix(prefix, csrs, done):
for csr in csrs:
if csr.huid not in done:
if csr.duid not in done:
csr.name = prefix + csr.name
done.add(csr.huid)
done.add(csr.duid)
def memprefix(prefix, memories, done):
for memory in memories:
if memory.huid not in done:
if memory.duid not in done:
memory.name_override = prefix + memory.name_override
done.add(memory.huid)
done.add(memory.duid)
def _make_gatherer(method, cls, prefix_cb):
@ -124,7 +124,7 @@ def _make_gatherer(method, cls, prefix_cb):
items = getattr(v, method)()
prefix_cb(k + "_", items, prefixed)
r += items
return sorted(r, key=lambda x: x.huid)
return sorted(r, key=lambda x: x.duid)
return gatherer

41
misoc/interconnect/csr_bus.py
View File

@ -1,10 +1,9 @@
from migen.fhdl.std import *
from migen.bus.transactions import *
from migen.bank.description import CSRStorage
from migen import *
from migen.genlib.record import *
from migen.genlib.misc import chooser
from misoc.interconnect import csr
from misoc.interconnect.csr import CSRStorage
_layout = [
@ -26,42 +25,6 @@ class Interconnect(Module):
self.comb += master.connect(*slaves)
class Initiator(Module):
def __init__(self, generator, bus=None):
self.generator = generator
if bus is None:
bus = Interface()
self.bus = bus
self.transaction = None
self.read_data_ready = False
self.done = False
def do_simulation(self, selfp):
if not self.done:
if self.transaction is not None:
if isinstance(self.transaction, TRead):
if self.read_data_ready:
self.transaction.data = selfp.bus.dat_r
self.transaction = None
self.read_data_ready = False
else:
self.read_data_ready = True
else:
selfp.bus.we = 0
self.transaction = None
if self.transaction is None:
try:
self.transaction = next(self.generator)
except StopIteration:
self.transaction = None
raise StopSimulation
if self.transaction is not None:
selfp.bus.adr = self.transaction.address
if isinstance(self.transaction, TWrite):
selfp.bus.we = 1
selfp.bus.dat_w = self.transaction.data
class SRAM(Module):
def __init__(self, mem_or_size, address, read_only=None, init=None, bus=None):
if bus is None:

19
misoc/interconnect/csr_eventmanager.py
View File

@ -1,12 +1,15 @@
from functools import reduce
from operator import or_
from migen import *
from migen.util.misc import xdir
from migen.fhdl.std import *
from migen.bank.description import *
from migen.genlib.misc import optree
from misoc.interconnect.csr import *
class _EventSource(HUID):
class _EventSource(DUID):
def __init__(self):
HUID.__init__(self)
DUID.__init__(self)
self.status = Signal() # value in the status register
self.pending = Signal() # value in the pending register + assert irq if unmasked
self.trigger = Signal() # trigger signal interface to the user design
@ -53,7 +56,7 @@ class EventManager(Module, AutoCSR):
def do_finalize(self):
sources_u = [v for k, v in xdir(self, True) if isinstance(v, _EventSource)]
sources = sorted(sources_u, key=lambda x: x.huid)
sources = sorted(sources_u, key=lambda x: x.duid)
n = len(sources)
self.status = CSR(n)
self.pending = CSR(n)
@ -67,7 +70,7 @@ class EventManager(Module, AutoCSR):
]
irqs = [self.pending.w[i] & self.enable.storage[i] for i in range(n)]
self.comb += self.irq.eq(optree("|", irqs))
self.comb += self.irq.eq(reduce(or_, irqs))
def __setattr__(self, name, value):
object.__setattr__(self, name, value)
@ -80,4 +83,4 @@ class EventManager(Module, AutoCSR):
class SharedIRQ(Module):
def __init__(self, *event_managers):
self.irq = Signal()
self.comb += self.irq.eq(optree("|", [ev.irq for ev in event_managers]))
self.comb += self.irq.eq(reduce(or_, [ev.irq for ev in event_managers]))

1
misoc/interconnect/dma_lasmi.py
View File

@ -1,5 +1,4 @@
from migen import *
from migen.flow.actor import *
from migen.genlib.fifo import SyncFIFO

274
misoc/interconnect/lasmi_bus.py
View File

@ -1,8 +1,9 @@
from functools import reduce
from operator import or_
from migen import *
from migen.bus.transactions import *
from migen.genlib import roundrobin
from migen.genlib.record import *
from migen.genlib.misc import optree
class Interface(Record):
@ -35,130 +36,173 @@ class Interface(Record):
Record.__init__(self, layout)
class Initiator(Module):
def __init__(self, generator, bus):
self.generator = generator
self.bus = bus
self.transaction_start = 0
self.transaction = None
self.transaction_end = None
def do_simulation(self, selfp):
selfp.bus.dat_w = 0
selfp.bus.dat_we = 0
if self.transaction is not None:
if selfp.bus.req_ack:
selfp.bus.stb = 0
if selfp.bus.dat_ack:
if isinstance(self.transaction, TRead):
self.transaction_end = selfp.simulator.cycle_counter + self.bus.read_latency
else:
self.transaction_end = selfp.simulator.cycle_counter + self.bus.write_latency - 1
if self.transaction is None or selfp.simulator.cycle_counter == self.transaction_end:
if self.transaction is not None:
self.transaction.latency = selfp.simulator.cycle_counter - self.transaction_start - 1
if isinstance(self.transaction, TRead):
self.transaction.data = selfp.bus.dat_r
else:
selfp.bus.dat_w = self.transaction.data
selfp.bus.dat_we = self.transaction.sel
try:
self.transaction = next(self.generator)
except StopIteration:
raise StopSimulation
if self.transaction is not None:
self.transaction_start = selfp.simulator.cycle_counter
selfp.bus.stb = 1
selfp.bus.adr = self.transaction.address
if isinstance(self.transaction, TRead):
selfp.bus.we = 0
else:
selfp.bus.we = 1
def _getattr_all(l, attr):
it = iter(l)
r = getattr(next(it), attr)
for e in it:
if getattr(e, attr) != r:
raise ValueError
return r
class TargetModel:
def __init__(self):
self.last_bank = 0
class LASMIxbar(Module):
def __init__(self, controllers, cba_shift):
self._controllers = controllers
self._cba_shift = cba_shift
def read(self, bank, address):
return 0
self._rca_bits = _getattr_all(controllers, "aw")
self._dw = _getattr_all(controllers, "dw")
self._nbanks = _getattr_all(controllers, "nbanks")
self._req_queue_size = _getattr_all(controllers, "req_queue_size")
self._read_latency = _getattr_all(controllers, "read_latency")
self._write_latency = _getattr_all(controllers, "write_latency")
def write(self, bank, address, data, we):
pass
self._bank_bits = log2_int(self._nbanks, False)
self._controller_bits = log2_int(len(self._controllers), False)
# Round-robin scheduling
def select_bank(self, pending_banks):
if not pending_banks:
return -1
self.last_bank += 1
if self.last_bank > max(pending_banks):
self.last_bank = 0
while self.last_bank not in pending_banks:
self.last_bank += 1
return self.last_bank
self._masters = []
def get_master(self):
if self.finalized:
raise FinalizeError
lasmi_master = Interface(self._rca_bits + self._bank_bits + self._controller_bits,
self._dw, 1, self._req_queue_size, self._read_latency, self._write_latency)
self._masters.append(lasmi_master)
return lasmi_master
class _ReqFIFO(Module):
def __init__(self, req_queue_size, bank):
self.req_queue_size = req_queue_size
self.bank = bank
self.contents = []
def do_finalize(self):
nmasters = len(self._masters)
def do_simulation(self, selfp):
if len(self.contents) < self.req_queue_size:
if selfp.bank.stb:
self.contents.append((selfp.bank.we, selfp.bank.adr))
selfp.bank.req_ack = 1
m_ca, m_ba, m_rca = self._split_master_addresses(self._controller_bits,
self._bank_bits, self._rca_bits, self._cba_shift)
for nc, controller in enumerate(self._controllers):
if self._controller_bits:
controller_selected = [ca == nc for ca in m_ca]
else:
controller_selected = [1]*nmasters
master_req_acks = [0]*nmasters
master_dat_w_acks = [0]*nmasters
master_dat_r_acks = [0]*nmasters
rrs = [roundrobin.RoundRobin(nmasters, roundrobin.SP_CE) for n in range(self._nbanks)]
self.submodules += rrs
for nb, rr in enumerate(rrs):
bank = getattr(controller, "bank"+str(nb))
# for each master, determine if another bank locks it
master_locked = []
for nm, master in enumerate(self._masters):
locked = 0
for other_nb, other_rr in enumerate(rrs):
if other_nb != nb:
other_bank = getattr(controller, "bank"+str(other_nb))
locked = locked | (other_bank.lock & (other_rr.grant == nm))
master_locked.append(locked)
# arbitrate
bank_selected = [cs & (ba == nb) & ~locked for cs, ba, locked in zip(controller_selected, m_ba, master_locked)]
bank_requested = [bs & master.stb for bs, master in zip(bank_selected, self._masters)]
self.comb += [
rr.request.eq(Cat(*bank_requested)),
rr.ce.eq(~bank.stb & ~bank.lock)
]
# route requests
self.comb += [
bank.adr.eq(Array(m_rca)[rr.grant]),
bank.we.eq(Array(self._masters)[rr.grant].we),
bank.stb.eq(Array(bank_requested)[rr.grant])
]
master_req_acks = [master_req_ack | ((rr.grant == nm) & bank_selected[nm] & bank.req_ack)
for nm, master_req_ack in enumerate(master_req_acks)]
master_dat_w_acks = [master_dat_w_ack | ((rr.grant == nm) & bank.dat_w_ack)
for nm, master_dat_w_ack in enumerate(master_dat_w_acks)]
master_dat_r_acks = [master_dat_r_ack | ((rr.grant == nm) & bank.dat_r_ack)
for nm, master_dat_r_ack in enumerate(master_dat_r_acks)]
for nm, master_dat_w_ack in enumerate(master_dat_w_acks):
for i in range(self._write_latency):
new_master_dat_w_ack = Signal()
self.sync += new_master_dat_w_ack.eq(master_dat_w_ack)
master_dat_w_ack = new_master_dat_w_ack
master_dat_w_acks[nm] = master_dat_w_ack
for nm, master_dat_r_ack in enumerate(master_dat_r_acks):
for i in range(self._read_latency):
new_master_dat_r_ack = Signal()
self.sync += new_master_dat_r_ack.eq(master_dat_r_ack)
master_dat_r_ack = new_master_dat_r_ack
master_dat_r_acks[nm] = master_dat_r_ack
self.comb += [master.req_ack.eq(master_req_ack) for master, master_req_ack in zip(self._masters, master_req_acks)]
self.comb += [master.dat_w_ack.eq(master_dat_w_ack) for master, master_dat_w_ack in zip(self._masters, master_dat_w_acks)]
self.comb += [master.dat_r_ack.eq(master_dat_r_ack) for master, master_dat_r_ack in zip(self._masters, master_dat_r_acks)]
# route data writes
controller_selected_wl = controller_selected
for i in range(self._write_latency):
n_controller_selected_wl = [Signal() for i in range(nmasters)]
self.sync += [n.eq(o) for n, o in zip(n_controller_selected_wl, controller_selected_wl)]
controller_selected_wl = n_controller_selected_wl
dat_w_maskselect = []
dat_we_maskselect = []
for master, selected in zip(self._masters, controller_selected_wl):
o_dat_w = Signal(self._dw)
o_dat_we = Signal(self._dw//8)
self.comb += If(selected,
o_dat_w.eq(master.dat_w),
o_dat_we.eq(master.dat_we)
)
dat_w_maskselect.append(o_dat_w)
dat_we_maskselect.append(o_dat_we)
self.comb += [
controller.dat_w.eq(reduce(or_, dat_w_maskselect)),
controller.dat_we.eq(reduce(or_, dat_we_maskselect))
]
# route data reads
if self._controller_bits:
for master in self._masters:
controller_sel = Signal(self._controller_bits)
for nc, controller in enumerate(self._controllers):
for nb in range(nbanks):
bank = getattr(controller, "bank"+str(nb))
self.comb += If(bank.stb & bank.ack, controller_sel.eq(nc))
for i in range(self._read_latency):
n_controller_sel = Signal(self._controller_bits)
self.sync += n_controller_sel.eq(controller_sel)
controller_sel = n_controller_sel
self.comb += master.dat_r.eq(Array(self._controllers)[controller_sel].dat_r)
else:
selfp.bank.req_ack = 0
selfp.bank.lock = bool(self.contents)
do_simulation.passive = True
self.comb += [master.dat_r.eq(self._controllers[0].dat_r) for master in self._masters]
class Target(Module):
def __init__(self, model, *ifargs, **ifkwargs):
self.model = model
self.bus = Interface(*ifargs, **ifkwargs)
self.req_fifos = [_ReqFIFO(self.bus.req_queue_size, getattr(self.bus, "bank"+str(nb)))
for nb in range(self.bus.nbanks)]
self.submodules += self.req_fifos
self.rd_pipeline = [None]*self.bus.read_latency
self.wr_pipeline = [None]*(self.bus.write_latency + 1)
def do_simulation(self, selfp):
# determine banks with pending requests
pending_banks = set(nb for nb, rf in enumerate(self.req_fifos) if rf.contents)
# issue new transactions
selected_bank_n = self.model.select_bank(pending_banks)
selected_transaction = None
for nb in range(self.bus.nbanks):
bank = getattr(selfp.bus, "bank"+str(nb))
if nb == selected_bank_n:
bank.dat_ack = 1
selected_transaction = self.req_fifos[nb].contents.pop(0)
def _split_master_addresses(self, controller_bits, bank_bits, rca_bits, cba_shift):
m_ca = [] # controller address
m_ba = [] # bank address
m_rca = [] # row and column address
for master in self._masters:
cba = Signal(self._controller_bits + self._bank_bits)
rca = Signal(self._rca_bits)
cba_upper = cba_shift + controller_bits + bank_bits
self.comb += cba.eq(master.adr[cba_shift:cba_upper])
if cba_shift < self._rca_bits:
if cba_shift:
self.comb += rca.eq(Cat(master.adr[:cba_shift], master.adr[cba_upper:]))
else:
self.comb += rca.eq(master.adr[cba_upper:])
else:
bank.dat_ack = 0
self.comb += rca.eq(master.adr[:cba_shift])
rd_transaction = None
wr_transaction = None
if selected_bank_n >= 0:
we, adr = selected_transaction
if we:
wr_transaction = selected_bank_n, adr
if self._controller_bits:
ca = Signal(self._controller_bits)
ba = Signal(self._bank_bits)
self.comb += Cat(ba, ca).eq(cba)
else:
rd_transaction = selected_bank_n, adr
ca = None
ba = cba
# data pipeline
self.rd_pipeline.append(rd_transaction)
self.wr_pipeline.append(wr_transaction)
done_rd_transaction = self.rd_pipeline.pop(0)
done_wr_transaction = self.wr_pipeline.pop(0)
if done_rd_transaction is not None:
selfp.bus.dat_r = self.model.read(done_rd_transaction[0], done_rd_transaction[1])
if done_wr_transaction is not None:
self.model.write(done_wr_transaction[0], done_wr_transaction[1],
selfp.bus.dat_w, selfp.bus.dat_we)
do_simulation.passive = True
m_ca.append(ca)
m_ba.append(ba)
m_rca.append(rca)
return m_ca, m_ba, m_rca

178
misoc/interconnect/lasmi_xbar.py
View File

@ -1,178 +0,0 @@
from migen import *
from migen.genlib import roundrobin
from migen.genlib.record import *
from migen.genlib.misc import optree
from misoc.mem.sdram.core.lasmibus import Interface
def _getattr_all(l, attr):
it = iter(l)
r = getattr(next(it), attr)
for e in it:
if getattr(e, attr) != r:
raise ValueError
return r
class LASMIxbar(Module):
def __init__(self, controllers, cba_shift):
self._controllers = controllers
self._cba_shift = cba_shift
self._rca_bits = _getattr_all(controllers, "aw")
self._dw = _getattr_all(controllers, "dw")
self._nbanks = _getattr_all(controllers, "nbanks")
self._req_queue_size = _getattr_all(controllers, "req_queue_size")
self._read_latency = _getattr_all(controllers, "read_latency")
self._write_latency = _getattr_all(controllers, "write_latency")
self._bank_bits = log2_int(self._nbanks, False)
self._controller_bits = log2_int(len(self._controllers), False)
self._masters = []
def get_master(self):
if self.finalized:
raise FinalizeError
lasmi_master = Interface(self._rca_bits + self._bank_bits + self._controller_bits,
self._dw, 1, self._req_queue_size, self._read_latency, self._write_latency)
self._masters.append(lasmi_master)
return lasmi_master
def do_finalize(self):
nmasters = len(self._masters)
m_ca, m_ba, m_rca = self._split_master_addresses(self._controller_bits,
self._bank_bits, self._rca_bits, self._cba_shift)
for nc, controller in enumerate(self._controllers):
if self._controller_bits:
controller_selected = [ca == nc for ca in m_ca]
else:
controller_selected = [1]*nmasters
master_req_acks = [0]*nmasters
master_dat_w_acks = [0]*nmasters
master_dat_r_acks = [0]*nmasters
rrs = [roundrobin.RoundRobin(nmasters, roundrobin.SP_CE) for n in range(self._nbanks)]
self.submodules += rrs
for nb, rr in enumerate(rrs):
bank = getattr(controller, "bank"+str(nb))
# for each master, determine if another bank locks it
master_locked = []
for nm, master in enumerate(self._masters):
locked = 0
for other_nb, other_rr in enumerate(rrs):
if other_nb != nb:
other_bank = getattr(controller, "bank"+str(other_nb))
locked = locked | (other_bank.lock & (other_rr.grant == nm))
master_locked.append(locked)
# arbitrate
bank_selected = [cs & (ba == nb) & ~locked for cs, ba, locked in zip(controller_selected, m_ba, master_locked)]
bank_requested = [bs & master.stb for bs, master in zip(bank_selected, self._masters)]
self.comb += [
rr.request.eq(Cat(*bank_requested)),
rr.ce.eq(~bank.stb & ~bank.lock)
]
# route requests
self.comb += [
bank.adr.eq(Array(m_rca)[rr.grant]),
bank.we.eq(Array(self._masters)[rr.grant].we),
bank.stb.eq(Array(bank_requested)[rr.grant])
]
master_req_acks = [master_req_ack | ((rr.grant == nm) & bank_selected[nm] & bank.req_ack)
for nm, master_req_ack in enumerate(master_req_acks)]
master_dat_w_acks = [master_dat_w_ack | ((rr.grant == nm) & bank.dat_w_ack)
for nm, master_dat_w_ack in enumerate(master_dat_w_acks)]
master_dat_r_acks = [master_dat_r_ack | ((rr.grant == nm) & bank.dat_r_ack)
for nm, master_dat_r_ack in enumerate(master_dat_r_acks)]
for nm, master_dat_w_ack in enumerate(master_dat_w_acks):
for i in range(self._write_latency):
new_master_dat_w_ack = Signal()
self.sync += new_master_dat_w_ack.eq(master_dat_w_ack)
master_dat_w_ack = new_master_dat_w_ack
master_dat_w_acks[nm] = master_dat_w_ack
for nm, master_dat_r_ack in enumerate(master_dat_r_acks):
for i in range(self._read_latency):
new_master_dat_r_ack = Signal()
self.sync += new_master_dat_r_ack.eq(master_dat_r_ack)
master_dat_r_ack = new_master_dat_r_ack
master_dat_r_acks[nm] = master_dat_r_ack
self.comb += [master.req_ack.eq(master_req_ack) for master, master_req_ack in zip(self._masters, master_req_acks)]
self.comb += [master.dat_w_ack.eq(master_dat_w_ack) for master, master_dat_w_ack in zip(self._masters, master_dat_w_acks)]
self.comb += [master.dat_r_ack.eq(master_dat_r_ack) for master, master_dat_r_ack in zip(self._masters, master_dat_r_acks)]
# route data writes
controller_selected_wl = controller_selected
for i in range(self._write_latency):
n_controller_selected_wl = [Signal() for i in range(nmasters)]
self.sync += [n.eq(o) for n, o in zip(n_controller_selected_wl, controller_selected_wl)]
controller_selected_wl = n_controller_selected_wl
dat_w_maskselect = []
dat_we_maskselect = []
for master, selected in zip(self._masters, controller_selected_wl):
o_dat_w = Signal(self._dw)
o_dat_we = Signal(self._dw//8)
self.comb += If(selected,
o_dat_w.eq(master.dat_w),
o_dat_we.eq(master.dat_we)
)
dat_w_maskselect.append(o_dat_w)
dat_we_maskselect.append(o_dat_we)
self.comb += [
controller.dat_w.eq(optree("|", dat_w_maskselect)),
controller.dat_we.eq(optree("|", dat_we_maskselect))
]
# route data reads
if self._controller_bits:
for master in self._masters:
controller_sel = Signal(self._controller_bits)
for nc, controller in enumerate(self._controllers):
for nb in range(nbanks):
bank = getattr(controller, "bank"+str(nb))
self.comb += If(bank.stb & bank.ack, controller_sel.eq(nc))
for i in range(self._read_latency):
n_controller_sel = Signal(self._controller_bits)
self.sync += n_controller_sel.eq(controller_sel)
controller_sel = n_controller_sel
self.comb += master.dat_r.eq(Array(self._controllers)[controller_sel].dat_r)
else:
self.comb += [master.dat_r.eq(self._controllers[0].dat_r) for master in self._masters]
def _split_master_addresses(self, controller_bits, bank_bits, rca_bits, cba_shift):
m_ca = [] # controller address
m_ba = [] # bank address
m_rca = [] # row and column address
for master in self._masters:
cba = Signal(self._controller_bits + self._bank_bits)
rca = Signal(self._rca_bits)
cba_upper = cba_shift + controller_bits + bank_bits
self.comb += cba.eq(master.adr[cba_shift:cba_upper])
if cba_shift < self._rca_bits:
if cba_shift:
self.comb += rca.eq(Cat(master.adr[:cba_shift], master.adr[cba_upper:]))
else:
self.comb += rca.eq(master.adr[cba_upper:])
else:
self.comb += rca.eq(master.adr[:cba_shift])
if self._controller_bits:
ca = Signal(self._controller_bits)
ba = Signal(self._bank_bits)
self.comb += Cat(ba, ca).eq(cba)
else:
ca = None
ba = cba
m_ca.append(ca)
m_ba.append(ba)
m_rca.append(rca)
return m_ca, m_ba, m_rca

105
misoc/interconnect/wishbone.py
View File

@ -1,13 +1,16 @@
from migen.fhdl.std import *
from functools import reduce
from operator import or_
from migen import *
from migen.genlib import roundrobin
from migen.genlib.record import *
from migen.genlib.misc import split, displacer, optree, chooser
from migen.genlib.misc import FlipFlop, Counter
from migen.genlib.misc import split, displacer, chooser
from migen.genlib.fsm import FSM, NextState
from migen.bus.transactions import *
from misoc.interconnect import csr
# TODO: rewrite without FlipFlop and Counter
_layout = [
("adr", 30, DIR_M_TO_S),
@ -94,13 +97,13 @@ class Decoder(Module):
# generate master ack (resp. err) by ORing all slave acks (resp. errs)
self.comb += [
master.ack.eq(optree("|", [slave[1].ack for slave in slaves])),
master.err.eq(optree("|", [slave[1].err for slave in slaves]))
master.ack.eq(reduce(or_, [slave[1].ack for slave in slaves])),
master.err.eq(reduce(or_, [slave[1].err for slave in slaves]))
]
# mux (1-hot) slave data return
masked = [Replicate(slave_sel_r[i], flen(master.dat_r)) & slaves[i][1].dat_r for i in range(ns)]
self.comb += master.dat_r.eq(optree("|", masked))
self.comb += master.dat_r.eq(reduce(or_, masked))
class InterconnectShared(Module):
@ -566,94 +569,6 @@ class Cache(Module):
)
class Tap(Module):
def __init__(self, bus, handler=print):
self.bus = bus
self.handler = handler
def do_simulation(self, selfp):
if selfp.bus.ack:
assert(selfp.bus.cyc and selfp.bus.stb)
if selfp.bus.we:
transaction = TWrite(selfp.bus.adr,
selfp.bus.dat_w,
selfp.bus.sel)
else:
transaction = TRead(selfp.bus.adr,
selfp.bus.dat_r)
self.handler(transaction)
do_simulation.passive = True
class Initiator(Module):
def __init__(self, generator, bus=None):
self.generator = generator
if bus is None:
bus = Interface()
self.bus = bus
self.transaction_start = 0
self.transaction = None
def do_simulation(self, selfp):
if self.transaction is None or selfp.bus.ack:
if self.transaction is not None:
self.transaction.latency = selfp.simulator.cycle_counter - self.transaction_start - 1
if isinstance(self.transaction, TRead):
self.transaction.data = selfp.bus.dat_r
try:
self.transaction = next(self.generator)
except StopIteration:
selfp.bus.cyc = 0
selfp.bus.stb = 0
raise StopSimulation
if self.transaction is not None:
self.transaction_start = selfp.simulator.cycle_counter
selfp.bus.cyc = 1
selfp.bus.stb = 1
selfp.bus.adr = self.transaction.address
if isinstance(self.transaction, TWrite):
selfp.bus.we = 1
selfp.bus.sel = self.transaction.sel
selfp.bus.dat_w = self.transaction.data
else:
selfp.bus.we = 0
else:
selfp.bus.cyc = 0
selfp.bus.stb = 0
class TargetModel:
def read(self, address):
return 0
def write(self, address, data, sel):
pass
def can_ack(self, bus):
return True
class Target(Module):
def __init__(self, model, bus=None):
if bus is None:
bus = Interface()
self.bus = bus
self.model = model
def do_simulation(self, selfp):
bus = selfp.bus
if not bus.ack:
if self.model.can_ack(bus) and bus.cyc and bus.stb:
if bus.we:
self.model.write(bus.adr, bus.dat_w, bus.sel)
else:
bus.dat_r = self.model.read(bus.adr)
bus.ack = 1
else:
bus.ack = 0
do_simulation.passive = True
class SRAM(Module):
def __init__(self, mem_or_size, read_only=None, init=None, bus=None):
if bus is None:

6
misoc/interconnect/wishbone2csr.py
View File

@ -1,8 +1,8 @@
from migen.fhdl.std import *
from migen.bus import wishbone
from migen.bus import csr
from migen import *
from migen.genlib.misc import timeline
from misoc.interconnect import csr, wishbone
class WB2CSR(Module):
def __init__(self, bus_wishbone=None, bus_csr=None):

1
misoc/interconnect/wishbone2lasmi.py
View File

@ -1,6 +1,7 @@
from migen import *
from migen.genlib.fsm import FSM, NextState
class WB2LASMI(Module):
def __init__(self, wishbone, lasmim):

16
targets/de0nano.py
View File

@ -1,9 +1,9 @@
from migen import *
from misoc.mem.sdram.module import IS42S16160
from misoc.mem.sdram.phy import gensdrphy
from misoc.mem.sdram.core.lasmicon import LASMIconSettings
from misoc.soc.sdram import SDRAMSoC
from misoc.cores.sdram_settings import IS42S16160
from misoc.cores.sdram_phy import GENSDRPHY
from misoc.cores.lasmicon.core import LASMIconSettings
from misoc.integration.soc_sdram import SoCSDRAM
class _PLL(Module):
@ -79,11 +79,11 @@ class _CRG(Module):
self.comb += platform.request("sdram_clock").eq(self.cd_sys_ps.clk)
class BaseSoC(SDRAMSoC):
class BaseSoC(SoCSDRAM):
default_platform = "de0nano"
def __init__(self, platform, sdram_controller_settings=LASMIconSettings(), **kwargs):
SDRAMSoC.__init__(self, platform,
SoCSDRAM.__init__(self, platform,
clk_freq=100*1000000,
integrated_rom_size=0x8000,
sdram_controller_settings=sdram_controller_settings,
@ -92,8 +92,8 @@ class BaseSoC(SDRAMSoC):
self.submodules.crg = _CRG(platform)
if not self.integrated_main_ram_size:
self.submodules.sdrphy = gensdrphy.GENSDRPHY(platform.request("sdram"),
IS42S16160(self.clk_freq))
self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"),
IS42S16160(self.clk_freq))
self.register_sdram_phy(self.sdrphy)
default_subtarget = BaseSoC

25
targets/kc705.py
View File

@ -1,15 +1,14 @@
from migen import *
from migen.genlib.resetsync import AsyncResetSynchronizer
from misoc.mem.sdram.module import MT8JTF12864
from misoc.mem.sdram.phy import k7ddrphy
from misoc.mem.sdram.core.lasmicon import LASMIconSettings
from misoc.mem.flash import spiflash
from misoc.soc import mem_decoder
from misoc.soc.sdram import SDRAMSoC
from misoc.com.liteethmini.phy import LiteEthPHY
from misoc.com.liteethmini.mac import LiteEthMAC
from misoc.cores.sdram_settings import MT8JTF12864
from misoc.cores.sdram_phy import k7ddrphy
from misoc.cores.lasmicon.core import LASMIconSettings
from misoc.cores import spi_flash
from misoc.cores.liteeth_mini.phy import LiteEthPHY
from misoc.cores.liteeth_mini.mac import LiteEthMAC
from misoc.integration.soc_core import mem_decoder
from misoc.integration.soc_sdram import SoCSDRAM
class _CRG(Module):
@ -69,17 +68,17 @@ class _CRG(Module):
self.specials += Instance("IDELAYCTRL", i_REFCLK=ClockSignal("clk200"), i_RST=ic_reset)
class BaseSoC(SDRAMSoC):
class BaseSoC(SoCSDRAM):
default_platform = "kc705"
csr_map = {
"spiflash": 16,
"ddrphy": 17,
}
csr_map.update(SDRAMSoC.csr_map)
csr_map.update(SoCSDRAM.csr_map)
def __init__(self, platform, sdram_controller_settings=LASMIconSettings(), **kwargs):
SDRAMSoC.__init__(self, platform,
SoCSDRAM.__init__(self, platform,
clk_freq=125*1000000, cpu_reset_address=0xaf0000,
sdram_controller_settings=sdram_controller_settings,
**kwargs)
@ -97,7 +96,7 @@ class BaseSoC(SDRAMSoC):
self.specials += Instance("STARTUPE2",
i_CLK=0, i_GSR=0, i_GTS=0, i_KEYCLEARB=0, i_PACK=0,
i_USRCCLKO=spiflash_pads.clk, i_USRCCLKTS=0, i_USRDONEO=1, i_USRDONETS=1)
self.submodules.spiflash = spiflash.SpiFlash(spiflash_pads, dummy=11, div=2)
self.submodules.spiflash = spi_flash.SpiFlash(spiflash_pads, dummy=11, div=2)
self.add_constant("SPIFLASH_PAGE_SIZE", 256)
self.add_constant("SPIFLASH_SECTOR_SIZE", 0x10000)
self.flash_boot_address = 0xb00000

18
targets/minispartan6.py
View File

@ -2,12 +2,12 @@ from fractions import Fraction
from migen import *
from migen.genlib.resetsync import AsyncResetSynchronizer
from migen.actorlib.fifo import SyncFIFO
from misoc.mem.sdram.module import AS4C16M16
from misoc.mem.sdram.phy import gensdrphy
from misoc.mem.sdram.core.lasmicon import LASMIconSettings
from misoc.soc.sdram import SDRAMSoC
from misoc.cores.sdram_settings import AS4C16M16
from misoc.cores.sdram_phy import GENSDRPHY
from misoc.cores.lasmicon.core import LASMIconSettings
from misoc.integration.soc_sdram import SoCSDRAM
class _CRG(Module):
def __init__(self, platform, clk_freq):
@ -60,12 +60,12 @@ class _CRG(Module):
o_Q=platform.request("sdram_clock"))
class BaseSoC(SDRAMSoC):
class BaseSoC(SoCSDRAM):
default_platform = "minispartan6"
def __init__(self, platform, sdram_controller_settings=LASMIconSettings(), **kwargs):
clk_freq = 80*1000000
SDRAMSoC.__init__(self, platform, clk_freq,
SoCSDRAM.__init__(self, platform, clk_freq,
integrated_rom_size=0x8000,
sdram_controller_settings=sdram_controller_settings,
**kwargs)
@ -73,8 +73,8 @@ class BaseSoC(SDRAMSoC):
self.submodules.crg = _CRG(platform, clk_freq)
if not self.integrated_main_ram_size:
self.submodules.sdrphy = gensdrphy.GENSDRPHY(platform.request("sdram"),
AS4C16M16(clk_freq))
self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"),
AS4C16M16(clk_freq))
self.register_sdram_phy(self.sdrphy)
default_subtarget = BaseSoC

39
targets/mlabs_video.py
View File

@ -3,18 +3,18 @@ from fractions import Fraction
from math import ceil
from migen import *
from mibuild.generic_platform import ConstraintError
from migen.build.generic_platform import ConstraintError
from misoc.mem.sdram.module import MT46V32M16
from misoc.mem.sdram.phy import s6ddrphy
from misoc.mem.sdram.core.lasmicon import LASMIconSettings
from misoc.mem.flash import norflash16
from misoc.video import framebuffer
from misoc.soc import mem_decoder
from misoc.soc.sdram import SDRAMSoC
from misoc.com import gpio
from misoc.com.liteethmini.phy import LiteEthPHY
from misoc.com.liteethmini.mac import LiteEthMAC
from misoc.cores.sdram_settings import MT46V32M16
from misoc.cores.sdram_phy import S6HalfRateDDRPHY
from misoc.cores.lasmicon.core import LASMIconSettings
from misoc.cores import nor_flash_16
from misoc.cores import framebuffer
from misoc.cores import gpio
from misoc.cores.liteeth_mini.phy import LiteEthPHY
from misoc.cores.liteeth_mini.mac import LiteEthMAC
from misoc.integration.soc_core import mem_decoder
from misoc.integration.soc_sdram import SoCSDRAM
class _MXCRG(Module):
@ -69,11 +69,11 @@ class _MXClockPads:
self.ddr_clk_n = ddram_clock.n
class BaseSoC(SDRAMSoC):
class BaseSoC(SoCSDRAM):
default_platform = "mixxeo" # also supports m1
def __init__(self, platform, sdram_controller_settings=LASMIconSettings(), **kwargs):
SDRAMSoC.__init__(self, platform,
SoCSDRAM.__init__(self, platform,
clk_freq=(83 + Fraction(1, 3))*1000000,
cpu_reset_address=0x00180000,
sdram_controller_settings=sdram_controller_settings,
@ -82,11 +82,11 @@ class BaseSoC(SDRAMSoC):
self.submodules.crg = _MXCRG(_MXClockPads(platform), self.clk_freq)
if not self.integrated_main_ram_size:
self.submodules.ddrphy = s6ddrphy.S6HalfRateDDRPHY(platform.request("ddram"),
MT46V32M16(self.clk_freq),
rd_bitslip=0,
wr_bitslip=3,
dqs_ddr_alignment="C1")
self.submodules.ddrphy = S6HalfRateDDRPHY(platform.request("ddram"),
MT46V32M16(self.clk_freq),
rd_bitslip=0,
wr_bitslip=3,
dqs_ddr_alignment="C1")
self.register_sdram_phy(self.ddrphy)
self.comb += [
self.ddrphy.clk4x_wr_strb.eq(self.crg.clk4x_wr_strb),
@ -95,7 +95,8 @@ class BaseSoC(SDRAMSoC):
if not self.integrated_rom_size:
clk_period_ns = 1000000000/self.clk_freq
self.submodules.norflash = norflash16.NorFlash16(platform.request("norflash"),
self.submodules.norflash = nor_flash_16.NorFlash16(
platform.request("norflash"),
ceil(110/clk_period_ns), ceil(50/clk_period_ns))
self.flash_boot_address = 0x001a0000
self.register_rom(self.norflash.bus)

30
targets/pipistrello.py
View File

@ -3,11 +3,11 @@ from fractions import Fraction
from migen import *
from migen.genlib.resetsync import AsyncResetSynchronizer
from misoc.mem.sdram.module import MT46H32M16
from misoc.mem.sdram.phy import s6ddrphy
from misoc.mem.sdram.core.lasmicon import LASMIconSettings
from misoc.mem.flash import spiflash
from misoc.soc.sdram import SDRAMSoC
from misoc.cores.sdram_settings import MT46H32M16
from misoc.cores.sdram_phy import S6HalfRateDDRPHY
from misoc.cores.lasmicon.core import LASMIconSettings
from misoc.cores import spi_flash
from misoc.integration.soc_sdram import SoCSDRAM
class _CRG(Module):
@ -90,17 +90,17 @@ class _CRG(Module):
o_Q=clk.n)
class BaseSoC(SDRAMSoC):
class BaseSoC(SoCSDRAM):
default_platform = "pipistrello"
csr_map = {
"spiflash": 16,
}
csr_map.update(SDRAMSoC.csr_map)
csr_map.update(SoCSDRAM.csr_map)
def __init__(self, platform, sdram_controller_settings=LASMIconSettings(),
clk_freq=(83 + Fraction(1, 3))*1000*1000, **kwargs):
SDRAMSoC.__init__(self, platform, clk_freq,
SoCSDRAM.__init__(self, platform, clk_freq,
cpu_reset_address=0x170000, # 1.5 MB
sdram_controller_settings=sdram_controller_settings,
**kwargs)
@ -108,11 +108,11 @@ class BaseSoC(SDRAMSoC):
self.submodules.crg = _CRG(platform, clk_freq)
if not self.integrated_main_ram_size:
self.submodules.ddrphy = s6ddrphy.S6HalfRateDDRPHY(platform.request("ddram"),
MT46H32M16(self.clk_freq),
rd_bitslip=1,
wr_bitslip=3,
dqs_ddr_alignment="C1")
self.submodules.ddrphy = S6HalfRateDDRPHY(platform.request("ddram"),
MT46H32M16(self.clk_freq),
rd_bitslip=1,
wr_bitslip=3,
dqs_ddr_alignment="C1")
self.comb += [
self.ddrphy.clk4x_wr_strb.eq(self.crg.clk4x_wr_strb),
self.ddrphy.clk4x_rd_strb.eq(self.crg.clk4x_rd_strb),
@ -120,8 +120,8 @@ class BaseSoC(SDRAMSoC):
self.register_sdram_phy(self.ddrphy)
if not self.integrated_rom_size:
self.submodules.spiflash = spiflash.SpiFlash(platform.request("spiflash4x"),
dummy=10, div=4)
self.submodules.spiflash = spi_flash.SpiFlash(platform.request("spiflash4x"),
dummy=10, div=4)
self.add_constant("SPIFLASH_PAGE_SIZE", 256)
self.add_constant("SPIFLASH_SECTOR_SIZE", 0x10000)
self.flash_boot_address = 0x180000

24
targets/ppro.py
View File

@ -3,11 +3,11 @@ from fractions import Fraction
from migen import *
from migen.genlib.resetsync import AsyncResetSynchronizer
from misoc.mem.sdram.module import MT48LC4M16
from misoc.mem.sdram.phy import gensdrphy
from misoc.mem.sdram.core.lasmicon import LASMIconSettings
from misoc.mem.flash import spiflash
from misoc.soc.sdram import SDRAMSoC
from misoc.cores.sdram_settings import MT48LC4M16
from misoc.cores.sdram_phy import GENSDRPHY
from misoc.cores.lasmicon.core import LASMIconSettings
from misoc.cores import spi_flash
from misoc.integration.soc_sdram import SoCSDRAM
class _CRG(Module):
@ -61,17 +61,17 @@ class _CRG(Module):
o_Q=platform.request("sdram_clock"))
class BaseSoC(SDRAMSoC):
class BaseSoC(SoCSDRAM):
default_platform = "papilio_pro"
csr_map = {
"spiflash": 16,
}
csr_map.update(SDRAMSoC.csr_map)
csr_map.update(SoCSDRAM.csr_map)
def __init__(self, platform, sdram_controller_settings=LASMIconSettings(), **kwargs):
clk_freq = 80*1000000
SDRAMSoC.__init__(self, platform, clk_freq,
SoCSDRAM.__init__(self, platform, clk_freq,
cpu_reset_address=0x60000,
sdram_controller_settings=sdram_controller_settings,
**kwargs)
@ -79,13 +79,13 @@ class BaseSoC(SDRAMSoC):
self.submodules.crg = _CRG(platform, clk_freq)
if not self.integrated_main_ram_size:
self.submodules.sdrphy = gensdrphy.GENSDRPHY(platform.request("sdram"),
MT48LC4M16(clk_freq))
self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"),
MT48LC4M16(clk_freq))
self.register_sdram_phy(self.sdrphy)
if not self.integrated_rom_size:
self.submodules.spiflash = spiflash.SpiFlash(platform.request("spiflash2x"),
dummy=4, div=6)
self.submodules.spiflash = spi_flash.SpiFlash(platform.request("spiflash2x"),
dummy=4, div=6)
self.flash_boot_address = 0x70000
self.register_rom(self.spiflash.bus)

11
targets/simple.py
View File

@ -1,15 +1,14 @@
from migen import *
from migen.bus import wishbone
from migen.genlib.io import CRG
from misoc.soc import SoC, mem_decoder
from misoc.com.liteethmini.phy import LiteEthPHY
from misoc.com.liteethmini.mac import LiteEthMAC
from misoc.cores.liteeth_mini.phy import LiteEthPHY
from misoc.cores.liteeth_mini.mac import LiteEthMAC
from misoc.integration.soc_core import SoCCore, mem_decoder
class BaseSoC(SoC):
class BaseSoC(SoCCore):
def __init__(self, platform, **kwargs):
SoC.__init__(self, platform,
SoCCore.__init__(self, platform,
clk_freq=int((1/(platform.default_clk_period))*1000000000),
integrated_rom_size=0x8000,
integrated_main_ram_size=16*1024,

7
targets/versa.py
View File

@ -1,14 +1,13 @@
from migen import *
from migen.bus import wishbone
from migen.genlib.io import CRG
from misoc.soc import SoC
from misoc.integration.soc_core import SoCCore
class BaseSoC(SoC):
class BaseSoC(SoCCore):
default_platform = "versa"
def __init__(self, platform, **kwargs):
SoC.__init__(self, platform,
SoCCore.__init__(self, platform,
clk_freq=100*1000000,
integrated_rom_size=0x8000,
**kwargs)