sim: enable relative include paths for verilator

2022-07-24 23:02:41 +02:00 · 2022-07-24 23:02:41 +02:00 · 7613c90fcd
parent b9a1fec30f
commit 7613c90fcd
1 changed files with 2 additions and 1 deletions
--- a/litex/build/sim/core/Makefile
+++ b/litex/build/sim/core/Makefile
@ -51,7 +51,8 @@ sim: $(OBJS_SIM) | mkdir
 		--output-split-ctrace 500 \
 		$(INC_DIR) \
 		-Wno-BLKANDNBLK \
-		-Wno-WIDTH
+		-Wno-WIDTH \
+		--relative-includes
 	make -j$(JOBS) -C $(OBJ_DIR) -f Vsim.mk Vsim

 .PHONY: modules