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soc/interconnect/stream/gearbox: inverse bit order

This commit is contained in:
Florent Kermarrec 2018-11-23 18:34:24 +01:00
parent d32e393033
commit 7623b5dd96
1 changed files with 2 additions and 2 deletions
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4
litex/soc/interconnect/stream.py
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@ -404,12 +404,12 @@ class Gearbox(Module):
i_cases = {} i_cases = {}
for i in range(io_lcm//i_dw): for i in range(io_lcm//i_dw):
i_cases[i] = shift_register[i_dw*i:i_dw*(i+1)].eq(sink.data) i_cases[i] = shift_register[i_dw*i:i_dw*(i+1)].eq(sink.data[::-1])
self.sync += If(sink.valid & sink.ready, Case(i_count, i_cases)) self.sync += If(sink.valid & sink.ready, Case(i_count, i_cases))
o_cases = {} o_cases = {}
for i in range(io_lcm//o_dw): for i in range(io_lcm//o_dw):
o_cases[i] = source.data.eq(shift_register[o_dw*i:o_dw*(i+1)]) o_cases[i] = source.data.eq(shift_register[o_dw*i:o_dw*(i+1)][::-1])
self.comb += Case(o_count, o_cases) self.comb += Case(o_count, o_cases)
# TODO: clean up code below # TODO: clean up code below