soc/cores/spi_flash: add missing endianness parameter

2018-11-23 18:33:53 +01:00 · 2018-11-23 18:33:53 +01:00 · d32e393033
parent c954943e02
commit d32e393033
1 changed files with 1 additions and 1 deletions
--- a/litex/soc/cores/spi_flash.py
+++ b/litex/soc/cores/spi_flash.py
@ -117,7 +117,7 @@ class SpiFlashDualQuad(Module, AutoCSR):


 class SpiFlashSingle(Module, AutoCSR):
-    def __init__(self, pads, dummy=15, div=2):
+    def __init__(self, pads, dummy=15, div=2, endianness="big"):
        """
        Simple SPI flash.
        Supports 1-bit reads. Only supports mode0 (cpol=0, cpha=0).