test/support: fix default ncycles
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0023b742e4
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7649028bdc
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@ -17,6 +17,6 @@ class SimCase:
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def test_to_verilog(self):
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def test_to_verilog(self):
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verilog.convert(self.tb)
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verilog.convert(self.tb)
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def run_with(self, cb, ncycles=-1):
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def run_with(self, cb, ncycles=None):
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self.tb.callback = cb
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self.tb.callback = cb
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run_simulation(self.tb, ncycles=ncycles)
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run_simulation(self.tb, ncycles=ncycles)
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