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Add new SocRegion mode "x" (executable) 

Defaults:
SoCRegion/SoCIORegion/SoCCSRRegion: RW
ROMs: RX
RAMs: RWX
This commit is contained in:
Christian Klarhorst 2022-08-30 15:57:25 +02:00
parent 37360587e3
commit 76c0754d1e
2 changed files with 3 additions and 3 deletions
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4
litex/soc/integration/soc.py
View File

@ -871,7 +871,7 @@ class SoC(Module):
colorer("added", color="green"))) colorer("added", color="green")))
setattr(self.submodules, name, SoCController(**kwargs)) setattr(self.submodules, name, SoCController(**kwargs))
def add_ram(self, name, origin, size, contents=[], mode="rw"): def add_ram(self, name, origin, size, contents=[], mode="rwx"):
ram_cls = { ram_cls = {
"wishbone": wishbone.SRAM, "wishbone": wishbone.SRAM,
"axi-lite": axi.AXILiteSRAM, "axi-lite": axi.AXILiteSRAM,
@ -894,7 +894,7 @@ class SoC(Module):
if contents != []: if contents != []:
self.add_config(f"{name}_INIT", 1) self.add_config(f"{name}_INIT", 1)
def add_rom(self, name, origin, size, contents=[], mode="r"): def add_rom(self, name, origin, size, contents=[], mode="rx"):
self.add_ram(name, origin, size, contents, mode=mode) self.add_ram(name, origin, size, contents, mode=mode)
def init_rom(self, name, contents=[], auto_size=True): def init_rom(self, name, contents=[], auto_size=True):

2
litex/soc/integration/soc_core.py
View File

@ -78,7 +78,7 @@ class SoCCore(LiteXSoC):
# ROM parameters # ROM parameters
integrated_rom_size = 0, integrated_rom_size = 0,
integrated_rom_mode = "r", integrated_rom_mode = "rx",
integrated_rom_init = [], integrated_rom_init = [],
# SRAM parameters # SRAM parameters