soc_core: fix missing init on main_ram

2020-02-19 14:58:55 +01:00 · 2020-02-19 14:58:55 +01:00 · 774a55a2aa
parent 5d580ca4e1
commit 774a55a2aa
1 changed files with 1 additions and 1 deletions
--- a/litex/soc/integration/soc_core.py
+++ b/litex/soc/integration/soc_core.py
@ -168,7 +168,7 @@ class SoCCore(LiteXSoC):

        # Add integrated MAIN_RAM (only useful when no external SRAM/SDRAM is available)
        if integrated_main_ram_size:
-            self.add_ram("main_ram", self.mem_map["main_ram"], integrated_main_ram_size)
+            self.add_ram("main_ram", self.mem_map["main_ram"], integrated_main_ram_size, integrated_main_ram_init)

        # Add Identifier
        if ident != "":