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soc_core: fix missing init on main_ram

This commit is contained in:
Florent Kermarrec 2020-02-19 14:58:55 +01:00
parent 5d580ca4e1
commit 774a55a2aa
1 changed files with 1 additions and 1 deletions
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2
litex/soc/integration/soc_core.py
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@ -168,7 +168,7 @@ class SoCCore(LiteXSoC):
# Add integrated MAIN_RAM (only useful when no external SRAM/SDRAM is available) # Add integrated MAIN_RAM (only useful when no external SRAM/SDRAM is available)
if integrated_main_ram_size: if integrated_main_ram_size:
self.add_ram("main_ram", self.mem_map["main_ram"], integrated_main_ram_size) self.add_ram("main_ram", self.mem_map["main_ram"], integrated_main_ram_size, integrated_main_ram_init)
# Add Identifier # Add Identifier
if ident != "": if ident != "":