gensoc: add check_cpu_memory_region and check_csr_region to detect csr and mem regions conflicts

misoclib/gensoc/__init__.py

@@ -91,10 +91,22 @@ class GenSoC(Module):
 			raise FinalizeError
 		self._wb_slaves.append((address_decoder, interface))
 
+	def check_cpu_memory_region(self, name, origin):
+		for n, o, l in self.cpu_memory_regions:
+			if n == name or o == origin:
+				raise ValueError("Memory region conflict between {} and {}".format(n, name))
+
 	def add_cpu_memory_region(self, name, origin, length):
+		self.check_cpu_memory_region(name, origin)
 		self.cpu_memory_regions.append((name, origin, length))
 
+	def check_cpu_csr_region(self, name, origin):
+		for n, o, l, obj in self.cpu_csr_regions:
+			if n == name or o == origin:
+				raise ValueError("CSR region conflict between {} and {}".format(n, name))
+
 	def add_cpu_csr_region(self, name, origin, busword, obj):
+		self.check_cpu_csr_region(name, origin)
 		self.cpu_csr_regions.append((name, origin, busword, obj))
 
 	def do_finalize(self):

targets/mlabs_video.py

@@ -128,7 +128,7 @@ TIMESPEC "TSise_sucks2" = FROM "GRPsys_clk" TO "GRPvga_clk" TIG;
 
 class FramebufferSoC(MiniSoC):
 	csr_map = {
-		"fb":					11,
+		"fb":					12,
 	}
 	csr_map.update(MiniSoC.csr_map)