cores/clocks/lattice_ecp5: Rename ECP5Delay to ECP5DynamicDelay and adapt style for consistency.
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@ -12,7 +12,7 @@ from litex.soc.cores.clock.intel_cyclone10 import Cyclone10LPPLL
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# Lattice
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# Lattice
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from litex.soc.cores.clock.lattice_ice40 import iCE40PLL
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from litex.soc.cores.clock.lattice_ice40 import iCE40PLL
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from litex.soc.cores.clock.lattice_ecp5 import ECP5PLL, ECP5Delay
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from litex.soc.cores.clock.lattice_ecp5 import ECP5PLL, ECP5DynamicDelay
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from litex.soc.cores.clock.lattice_nx import NXOSCA, NXPLL
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from litex.soc.cores.clock.lattice_nx import NXOSCA, NXPLL
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# Efinix
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# Efinix
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@ -10,7 +10,7 @@ from migen.genlib.resetsync import AsyncResetSynchronizer
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from litex.soc.cores.clock.common import *
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from litex.soc.cores.clock.common import *
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# Lattice / ECP5 -----------------------------------------------------------------------------------
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# Lattice / ECP5 PLL -------------------------------------------------------------------------------
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class ECP5PLL(Module):
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class ECP5PLL(Module):
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nclkouts_max = 4
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nclkouts_max = 4
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@ -166,50 +166,60 @@ class ECP5PLL(Module):
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self.params["attr"].append((f"FREQUENCY_PIN_CLKO{n_to_l[n]}", str(f/1e6)))
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self.params["attr"].append((f"FREQUENCY_PIN_CLKO{n_to_l[n]}", str(f/1e6)))
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self.specials += Instance("EHXPLLL", **self.params)
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self.specials += Instance("EHXPLLL", **self.params)
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# Lattice / ECP5 Dynamic Delay ---------------------------------------------------------------------
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class ECP5Delay(Module):
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class ECP5DynamicDelay(Module):
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# from ECP5 docs
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tap_delay = 25e-12
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delay_step_s = 25e-12
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ntaps = 128
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n_steps = 128
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def __init__(self):
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def __init__(self, i=None, o=None, taps=None):
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self.i = Signal()
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self.i = Signal() if i is None else i
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self.o = Signal()
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self.o = Signal() if o is None else o
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self.value = Signal(max=self.n_steps)
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self.taps = Signal(max=self.ntaps) if taps is None else taps
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def do_finalize(self):
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# # #
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rst = Signal()
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move = Signal()
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current_value = Signal(max=self.n_steps)
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self.specials += Instance(
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rst = Signal()
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"DELAYF",
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move = Signal()
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p_DEL_MODE="USER_DEFINED",
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done = Signal()
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p_DEL_VALUE=self.value.reset,
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change = Signal()
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i_A=self.i,
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curr_taps = Signal(max=self.ntaps)
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o_Z=self.o,
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i_LOADN=~(ResetSignal() | rst),
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# DELAYF Instance.
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i_MOVE=move,
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self.specials += Instance("DELAYF",
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i_DIRECTION=0,
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p_DEL_MODE = "USER_DEFINED",
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o_CFLAG=Signal()
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p_DEL_VALUE = self.taps.reset,
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i_A = self.i,
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o_Z = self.o,
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i_LOADN = ~(ResetSignal() | rst),
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i_MOVE = move,
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i_DIRECTION = 0,
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o_CFLAG = Signal()
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)
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)
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self.submodules.fsm = fsm = FSM()
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# FSM.
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fsm.act("WAIT",
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self.comb += done.eq( self.taps == curr_taps)
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If(self.value != current_value,
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self.comb += change.eq(self.taps != curr_taps)
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NextState('RST'))
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self.submodules.fsm = fsm = FSM(reset_state="IDLE")
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fsm.act("IDLE",
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If(change,
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NextState("DELAYF-RST")
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)
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)
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fsm.act("DELAYF-RST",
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rst.eq(1),
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NextValue(move, 0),
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NextValue(curr_taps, 0),
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NextState("DELAYF-MOVE")
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)
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fsm.act("DELAYF-MOVE",
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If(done,
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NextValue(move, 0),
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NextState("IDLE")
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).Else(
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NextValue(move, ~move),
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If(move,
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NextValue(curr_taps, curr_taps + 1)
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)
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)
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fsm.act("RST",
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)
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rst.eq(1),
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)
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NextValue(current_value, 0),
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NextState("MOVE")
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)
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fsm.act("MOVE",
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If(current_value == self.value,
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NextValue(move, 0),
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NextState("WAIT")
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).Else(
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NextValue(move, ~move),
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If(move,
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NextValue(current_value, current_value + 1)),
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))
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@ -130,8 +130,9 @@ class TestClock(unittest.TestCase):
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pll.create_clkout(ClockDomain("clkout4"), 175e6)
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pll.create_clkout(ClockDomain("clkout4"), 175e6)
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pll.compute_config()
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pll.compute_config()
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def test_ecp5_delay(self):
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def test_ecp5_dynamic_delay(self):
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delay = ECP5Delay()
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delay = ECP5DynamicDelay(i=Signal(), o=Signal(), taps=Signal(7))
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delay = ECP5DynamicDelay()
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# Lattice / NX
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# Lattice / NX
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def test_nxpll(self):
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def test_nxpll(self):
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