Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

command_tb: add random (still something to fix on TX)

This commit is contained in:
Florent Kermarrec 2014-12-14 16:38:38 +01:00
parent 46a39b7d41
commit 79e82d6ccd
2 changed files with 12 additions and 9 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

17
lib/sata/test/command_tb.py
View File

@ -106,7 +106,7 @@ class TB(Module):
def __init__(self): def __init__(self):
self.submodules.hdd = HDD( self.submodules.hdd = HDD(
phy_debug=False, phy_debug=False,
link_random_level=0, link_debug=False, link_random_level=25, link_debug=False,
transport_debug=False, transport_loopback=False, transport_debug=False, transport_loopback=False,
command_debug=False, command_debug=False,
mem_debug=True) mem_debug=True)
@ -115,17 +115,20 @@ class TB(Module):
self.submodules.command = SATACommand(self.transport) self.submodules.command = SATACommand(self.transport)
self.submodules.streamer = CommandStreamer() self.submodules.streamer = CommandStreamer()
streamer_ack_randomizer = AckRandomizer(command_tx_description(32), level=0)
self.submodules += streamer_ack_randomizer
self.submodules.logger = CommandLogger() self.submodules.logger = CommandLogger()
logger_ack_randomizer = AckRandomizer(command_rx_description(32), level=25)
self.submodules += logger_ack_randomizer
self.comb += [ self.comb += [
Record.connect(self.streamer.source, self.command.sink), Record.connect(self.streamer.source, streamer_ack_randomizer.sink),
Record.connect(self.command.source, self.logger.sink) Record.connect(streamer_ack_randomizer.source, self.command.sink),
Record.connect(self.command.source, logger_ack_randomizer.sink),
Record.connect(logger_ack_randomizer.source, self.logger.sink)
] ]
def gen_simulation(self, selfp): def gen_simulation(self, selfp):
self.hdd.allocate_mem(0x00000000, 64*1024*1024) self.hdd.allocate_mem(0x00000000, 64*1024*1024)
selfp.command.source.ack = 1
for i in range(100):
yield
write_data = [i for i in range(128)] write_data = [i for i in range(128)]
write_packet = CommandTXPacket(write=1, address=1024, length=len(write_data), data=write_data) write_packet = CommandTXPacket(write=1, address=1024, length=len(write_data), data=write_data)
yield from self.streamer.send(write_packet) yield from self.streamer.send(write_packet)
@ -141,4 +144,4 @@ class TB(Module):
print("shift "+ str(s) + " / length " + str(l) + " / errors " + str(e)) print("shift "+ str(s) + " / length " + str(l) + " / errors " + str(e))
if __name__ == "__main__": if __name__ == "__main__":
run_simulation(TB(), ncycles=512, vcd_name="my.vcd", keep_files=True) run_simulation(TB(), ncycles=1024, vcd_name="my.vcd", keep_files=True)

4
lib/sata/transport/__init__.py
View File

@ -60,7 +60,7 @@ class SATATransportTX(Module):
fsm.act("SEND_REG_H2D_CMD", fsm.act("SEND_REG_H2D_CMD",
_encode_cmd(sink, fis_reg_h2d_layout, encoded_cmd), _encode_cmd(sink, fis_reg_h2d_layout, encoded_cmd),
cmd_len.eq(fis_reg_h2d_cmd_len-1), cmd_len.eq(fis_reg_h2d_cmd_len-1),
cmd_send.eq(1), cmd_send.eq(sink.stb),
If(cmd_done, If(cmd_done,
sink.ack.eq(1), sink.ack.eq(1),
NextState("IDLE") NextState("IDLE")
@ -70,7 +70,7 @@ class SATATransportTX(Module):
_encode_cmd(sink, fis_data_layout, encoded_cmd), _encode_cmd(sink, fis_data_layout, encoded_cmd),
cmd_len.eq(fis_data_cmd_len-1), cmd_len.eq(fis_data_cmd_len-1),
cmd_with_data.eq(1), cmd_with_data.eq(1),
cmd_send.eq(1), cmd_send.eq(sink.stb),
If(cmd_done, If(cmd_done,
NextState("SEND_DATA") NextState("SEND_DATA")
) )