targets/nexys4ddr: add ethernet via method instead of inheritance
Switch adding LiteETH support to BaseSoc via a method instead of inheritance. This allows further optional peripherals to be added in the future, via additional methods. Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
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@ -66,18 +66,12 @@ class BaseSoC(SoCSDRAM):
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geom_settings = sdram_module.geom_settings,
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geom_settings = sdram_module.geom_settings,
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timing_settings = sdram_module.timing_settings)
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timing_settings = sdram_module.timing_settings)
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# EthernetSoC --------------------------------------------------------------------------------------
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def add_ethernet(self):
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mem_map = {
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"ethmac": 0xb0000000,
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}
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mem_map.update(self.mem_map)
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class EthernetSoC(BaseSoC):
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mem_map = {
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"ethmac": 0xb0000000,
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}
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mem_map.update(BaseSoC.mem_map)
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def __init__(self, **kwargs):
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BaseSoC.__init__(self, **kwargs)
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# Ethernet ---------------------------------------------------------------------------------
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# phy
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# phy
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self.submodules.ethphy = LiteEthPHYRMII(
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self.submodules.ethphy = LiteEthPHYRMII(
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clock_pads = self.platform.request("eth_clocks"),
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clock_pads = self.platform.request("eth_clocks"),
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@ -113,8 +107,9 @@ def main():
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help="enable Ethernet support")
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help="enable Ethernet support")
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args = parser.parse_args()
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args = parser.parse_args()
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cls = EthernetSoC if args.with_ethernet else BaseSoC
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soc = BaseSoC(sys_clk_freq=int(float(args.sys_clk_freq)), **soc_sdram_argdict(args))
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soc = cls(sys_clk_freq=int(float(args.sys_clk_freq)), **soc_sdram_argdict(args))
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if args.with_ethernet:
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soc.add_ethernet()
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builder = Builder(soc, **builder_argdict(args))
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builder = Builder(soc, **builder_argdict(args))
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builder.build()
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builder.build()
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