targets/nexys4ddr: add ethernet via method instead of inheritance

Switch adding LiteETH support to BaseSoc via a method instead of
inheritance. This allows further optional peripherals to be added
in the future, via additional methods.

Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
This commit is contained in:
Gabriel Somlo 2020-02-19 20:10:32 -05:00
parent 774a55a2aa
commit 7a2e33b817
1 changed files with 8 additions and 13 deletions

View File

@ -66,18 +66,12 @@ class BaseSoC(SoCSDRAM):
geom_settings = sdram_module.geom_settings, geom_settings = sdram_module.geom_settings,
timing_settings = sdram_module.timing_settings) timing_settings = sdram_module.timing_settings)
# EthernetSoC -------------------------------------------------------------------------------------- def add_ethernet(self):
mem_map = {
"ethmac": 0xb0000000,
}
mem_map.update(self.mem_map)
class EthernetSoC(BaseSoC):
mem_map = {
"ethmac": 0xb0000000,
}
mem_map.update(BaseSoC.mem_map)
def __init__(self, **kwargs):
BaseSoC.__init__(self, **kwargs)
# Ethernet ---------------------------------------------------------------------------------
# phy # phy
self.submodules.ethphy = LiteEthPHYRMII( self.submodules.ethphy = LiteEthPHYRMII(
clock_pads = self.platform.request("eth_clocks"), clock_pads = self.platform.request("eth_clocks"),
@ -113,8 +107,9 @@ def main():
help="enable Ethernet support") help="enable Ethernet support")
args = parser.parse_args() args = parser.parse_args()
cls = EthernetSoC if args.with_ethernet else BaseSoC soc = BaseSoC(sys_clk_freq=int(float(args.sys_clk_freq)), **soc_sdram_argdict(args))
soc = cls(sys_clk_freq=int(float(args.sys_clk_freq)), **soc_sdram_argdict(args)) if args.with_ethernet:
soc.add_ethernet()
builder = Builder(soc, **builder_argdict(args)) builder = Builder(soc, **builder_argdict(args))
builder.build() builder.build()