soc/integration/soc_dram: sync with litedram
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@ -25,7 +25,7 @@ class ControllerInjector(Module, AutoCSR):
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controller_settings)
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self.comb += controller.dfi.connect(self.dfii.slave)
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self.submodules.crossbar = crossbar.LiteDRAMCrossbar(controller.lasmic, controller.nrowbits)
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self.submodules.crossbar = crossbar.LiteDRAMCrossbar(controller.interface, controller.nrowbits)
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class SoCSDRAM(SoCCore):
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