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boards/targets/sim: update litedram
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@ -13,7 +13,7 @@ from litex.soc.cores import uart
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from litex.soc.integration.soc_core import mem_decoder
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from litedram.modules import PhySettings, IS42S16160
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from litedram.model import SDRAMPHYModel
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from litedram.phy.model import SDRAMPHYModel
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from liteeth.phy.model import LiteEthPHYModel
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from liteeth.core.mac import LiteEthMAC
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