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Fix ECP5PLL VCO frequency range 

See https://www.latticesemi.com/view_document?document_id=50461 ("ECP5
and ECP5-5G Family Data Sheet"), section 3.19 "sysCLOCK PLL Timing".
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Xiretza 2020-02-24 14:39:44 +01:00
parent 0c7e0bf025
commit 7a87d4e262
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litex/soc/cores/clock.py
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@ -507,7 +507,7 @@ class ECP5PLL(Module):
clko_div_range = (1, 128+1) clko_div_range = (1, 128+1)
clki_freq_range = ( 8e6, 400e6) clki_freq_range = ( 8e6, 400e6)
clko_freq_range = (3.125e6, 400e6) clko_freq_range = (3.125e6, 400e6)
vco_freq_range = ( 550e6, 1250e6) vco_freq_range = ( 400e6, 800e6)
def __init__(self): def __init__(self):
self.reset = Signal() self.reset = Signal()