Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Merge pull request #1183 from trabucayre/fix_yosys_synth 

litex/soc/cores/clock/xilinx_common: fix yosys synth: replace FD by FDCE
This commit is contained in:
enjoy-digital 2022-01-25 22:26:18 +01:00 committed by GitHub
parent 77c6cdd78e f8acc5f506
commit 7acdac2e51
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
litex/soc/cores/clock/xilinx_common.py
View File

@ -145,7 +145,7 @@ class XilinxClocking(Module, AutoCSR):
def add_reset_delay(self, cycles): def add_reset_delay(self, cycles):
for i in range(cycles): for i in range(cycles):
reset = Signal() reset = Signal()
self.specials += Instance("FD", i_C=self.clkin, i_D=self.reset, o_Q=reset) self.specials += Instance("FDCE", i_C=self.clkin, i_CE=1, i_CLR=0, i_D=self.reset, o_Q=reset)
self.reset = reset self.reset = reset
def do_finalize(self): def do_finalize(self):