litex/soc/cores/clock/xilinx_common: fix yosys synth: replace FD by FDCE

2022-01-25 21:44:02 +01:00 · 2022-01-25 21:44:02 +01:00 · f8acc5f506
parent 77c6cdd78e
commit f8acc5f506
1 changed files with 1 additions and 1 deletions
--- a/litex/soc/cores/clock/xilinx_common.py
+++ b/litex/soc/cores/clock/xilinx_common.py
@ -145,7 +145,7 @@ class XilinxClocking(Module, AutoCSR):
    def add_reset_delay(self, cycles):
        for i in range(cycles):
            reset = Signal()
-            self.specials += Instance("FD", i_C=self.clkin, i_D=self.reset, o_Q=reset)
+            self.specials += Instance("FDCE", i_C=self.clkin, i_CE=1, i_CLR=0, i_D=self.reset, o_Q=reset)
            self.reset = reset

    def do_finalize(self):