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Merge pull request #1183 from trabucayre/fix_yosys_synth 

litex/soc/cores/clock/xilinx_common: fix yosys synth: replace FD by FDCE
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enjoy-digital 2022-01-25 22:26:18 +01:00 committed by GitHub
parent 77c6cdd78e f8acc5f506
commit 7acdac2e51
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1 changed files with 1 additions and 1 deletions
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litex/soc/cores/clock/xilinx_common.py
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@ -145,7 +145,7 @@ class XilinxClocking(Module, AutoCSR):
def add_reset_delay(self, cycles):
for i in range(cycles):
reset = Signal()
self.specials += Instance("FD", i_C=self.clkin, i_D=self.reset, o_Q=reset)
self.specials += Instance("FDCE", i_C=self.clkin, i_CE=1, i_CLR=0, i_D=self.reset, o_Q=reset)
self.reset = reset
def do_finalize(self):