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cores/pwm: Simplify pwm generation and avoid potential glitch on reset.
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1 changed files with 1 additions and 8 deletions
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@ -47,14 +47,7 @@ class PWM(Module, AutoCSR):
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]
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# PWM Width logic.
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sync += [
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pwm.eq(0),
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If(self.enable & ~self.reset,
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If(counter < self.width,
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pwm.eq(1)
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)
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)
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]
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sync += pwm.eq(self.enable & (counter < self.width))
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if with_csr:
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self.add_csr(clock_domain)
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