cpu: remove initial SERV support (we'll work in a branch to experiment with it)
This commit is contained in:
Florent Kermarrec
parent
63a813af9c
commit
7b72148c4e
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@ -22,6 +22,3 @@
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[submodule "litex/soc/cores/cpu/rocket/verilog"]
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path = litex/soc/cores/cpu/rocket/verilog
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url = https://github.com/enjoy-digital/rocket-litex-verilog
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[submodule "litex/soc/cores/cpu/serv/verilog"]
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path = litex/soc/cores/cpu/serv/verilog
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url = https://github.com/olofk/serv
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@ -30,7 +30,6 @@ from litex.soc.cores.cpu.picorv32 import PicoRV32
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from litex.soc.cores.cpu.vexriscv import VexRiscv
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from litex.soc.cores.cpu.minerva import Minerva
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from litex.soc.cores.cpu.rocket import RocketRV64
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from litex.soc.cores.cpu.serv import SERV
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CPUS = {
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"lm32" : LM32,
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@ -39,7 +38,6 @@ CPUS = {
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"vexriscv" : VexRiscv,
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"minerva" : Minerva,
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"rocket" : RocketRV64,
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"serv" : SERV
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}
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# CPU Variants/Extensions Definition ---------------------------------------------------------------
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@ -1 +0,0 @@
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from litex.soc.cores.cpu.serv.core import SERV
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@ -1,96 +0,0 @@
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# This file is Copyright (c) 2019 Florent Kermarrec <florent@enjoy-digital.fr>
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# License: BSD
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import os
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from migen import *
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from litex.soc.interconnect import wishbone
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from litex.soc.cores.cpu import CPU
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CPU_VARIANTS = ["standard"]
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class SERV(CPU):
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name = "serv"
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data_width = 32
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endianness = "little"
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gcc_triple = ("riscv64-unknown-elf", "riscv32-unknown-elf")
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linker_output_format = "elf32-littleriscv"
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@property
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def gcc_triple(self):
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return ("riscv64-unknown-elf", "riscv32-unknown-elf")
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@property
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def gcc_flags(self):
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flags = "-march=rv32i "
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flags += "-mabi=ilp32 "
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flags += "-D__serv__ "
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return flags
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@property
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def linker_output_format(self):
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return "elf32-littleriscv"
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def __init__(self, platform, variant="standard"):
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assert variant is "standard", "Unsupported variant %s" % variant
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self.platform = platform
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self.variant = variant
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self.reset = Signal()
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self.ibus = wishbone.Interface()
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self.dbus = wishbone.Interface()
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self.interrupt = Signal(32)
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# # #
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self.cpu_params = dict(
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# clock / reset
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i_clk = ClockSignal(),
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i_i_rst = ResetSignal(),
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# timer irq
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i_i_timer_irq = 0,
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# ibus
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o_o_ibus_adr = self.ibus.adr,
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o_o_ibus_cyc = self.ibus.cyc,
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i_i_ibus_rdt = self.ibus.dat_r,
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i_i_ibus_ack = self.ibus.ack,
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# dbus
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o_o_dbus_adr = self.dbus.adr,
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o_o_dbus_dat = self.dbus.dat_w,
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o_o_dbus_sel = self.dbus.sel,
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o_o_dbus_we = self.dbus.we,
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o_o_dbus_cyc = self.dbus.cyc,
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i_i_dbus_rdt = self.dbus.dat_r,
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i_i_dbus_ack = self.dbus.ack,
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)
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self.comb += [
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self.ibus.stb.eq(self.ibus.cyc),
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self.dbus.stb.eq(self.dbus.cyc),
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]
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# add verilog sources
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self.add_sources(platform)
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def set_reset_address(self, reset_address):
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assert not hasattr(self, "reset_address")
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self.reset_address = reset_address
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self.cpu_params.update(p_RESET_PC=reset_address)
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@staticmethod
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def add_sources(platform):
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vdir = os.path.join(
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os.path.abspath(os.path.dirname(__file__)),
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"verilog", "rtl")
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platform.add_source_dir(vdir)
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platform.add_verilog_include_path(vdir)
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def do_finalize(self):
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assert hasattr(self, "reset_address")
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self.specials += Instance("serv_top", **self.cpu_params)
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@ -1,4 +0,0 @@
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.section .text, "ax", @progbits
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.global boot_helper
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boot_helper:
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jr x13
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@ -44,8 +44,6 @@ __attribute__((unused)) static void cdelay(int i)
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__asm__ volatile("nop");
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#elif defined (__powerpc__)
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__asm__ volatile("nop");
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#elif defined (__serv__)
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__asm__ volatile("nop");
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#else
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#error Unsupported architecture
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#endif
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@ -56,8 +56,6 @@ static inline unsigned int irq_getie(void)
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return (csrr(mstatus) & CSR_MSTATUS_MIE) != 0;
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#elif defined (__rocket__)
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return (csrr(mstatus) & CSR_MSTATUS_MIE) != 0;
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#elif defined (__serv__)
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return 0; /* FIXME */
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#else
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#error Unsupported architecture
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#endif
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@ -83,8 +81,6 @@ static inline void irq_setie(unsigned int ie)
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if(ie) csrs(mstatus,CSR_MSTATUS_MIE); else csrc(mstatus,CSR_MSTATUS_MIE);
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#elif defined (__rocket__)
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if(ie) csrs(mstatus,CSR_MSTATUS_MIE); else csrc(mstatus,CSR_MSTATUS_MIE);
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#elif defined (__serv__)
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/* FIXME */
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#else
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#error Unsupported architecture
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#endif
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@ -112,8 +108,6 @@ static inline unsigned int irq_getmask(void)
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return mask;
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#elif defined (__rocket__)
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return csr_readl(PLIC_ENABLED) >> 1;
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#elif defined (__serv__)
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return 0; /* FIXME */
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#else
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#error Unsupported architecture
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#endif
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@ -135,8 +129,6 @@ static inline void irq_setmask(unsigned int mask)
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asm volatile ("csrw %0, %1" :: "i"(CSR_IRQ_MASK), "r"(mask));
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#elif defined (__rocket__)
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csr_writel(mask << 1, PLIC_ENABLED);
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#elif defined (__serv__)
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/* FIXME */
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#else
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#error Unsupported architecture
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#endif
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@ -162,8 +154,6 @@ static inline unsigned int irq_pending(void)
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return pending;
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#elif defined (__rocket__)
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return csr_readl(PLIC_PENDING) >> 1;
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#elif defined (__serv__)
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return 0;/* FIXME */
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#else
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#error Unsupported architecture
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#endif
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@ -1,63 +0,0 @@
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#define MIE_MEIE 0x800
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.global _start
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_start:
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j reset_vector
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reset_vector:
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la sp, _fstack
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la t0, trap_vector
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csrw mtvec, t0
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// initialize .bss
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la t0, _fbss
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la t1, _ebss
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1: beq t0, t1, 2f
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sw zero, 0(t0)
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addi t0, t0, 4
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j 1b
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2:
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// enable external interrupts
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li t0, MIE_MEIE
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csrs mie, t0
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call main
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1: j 1b
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trap_vector:
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addi sp, sp, -16*4
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sw ra, 0*4(sp)
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sw t0, 1*4(sp)
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sw t1, 2*4(sp)
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sw t2, 3*4(sp)
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sw a0, 4*4(sp)
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sw a1, 5*4(sp)
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sw a2, 6*4(sp)
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sw a3, 7*4(sp)
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sw a4, 8*4(sp)
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sw a5, 9*4(sp)
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sw a6, 10*4(sp)
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sw a7, 11*4(sp)
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sw t3, 12*4(sp)
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sw t4, 13*4(sp)
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sw t5, 14*4(sp)
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sw t6, 15*4(sp)
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call isr
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lw ra, 0*4(sp)
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lw t0, 1*4(sp)
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lw t1, 2*4(sp)
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lw t2, 3*4(sp)
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lw a0, 4*4(sp)
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lw a1, 5*4(sp)
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lw a2, 6*4(sp)
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lw a3, 7*4(sp)
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lw a4, 8*4(sp)
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lw a5, 9*4(sp)
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lw a6, 10*4(sp)
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lw a7, 11*4(sp)
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lw t3, 12*4(sp)
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lw t4, 13*4(sp)
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lw t5, 14*4(sp)
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lw t6, 15*4(sp)
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addi sp, sp, 16*4
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mret
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@ -56,9 +56,6 @@ void flush_cpu_icache(void)
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#elif defined (__rocket__)
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/* FIXME: do something useful here! */
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asm volatile("nop");
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#elif defined (__serv__)
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/* no instruction cache */
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asm volatile("nop");
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#else
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#error Unsupported architecture
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#endif
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@ -104,9 +101,6 @@ void flush_cpu_dcache(void)
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#elif defined (__rocket__)
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/* FIXME: do something useful here! */
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asm volatile("nop");
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#elif defined (__serv__)
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/* no data cache */
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asm volatile("nop");
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#else
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#error Unsupported architecture
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#endif
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