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cpu/vexiiriscv update

This commit is contained in:
Dolu1990 2024-05-14 11:41:21 +02:00
parent 588b7a9519
commit 7b7334fc17
1 changed files with 1 additions and 1 deletions
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2
litex/soc/cores/cpu/vexiiriscv/core.py
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@ -130,7 +130,7 @@ class VexiiRiscv(CPU):
print(args) print(args)
if args.update_repo != "no": if args.update_repo != "no":
NaxRiscv.git_setup("VexiiRiscv", ndir, "https://github.com/SpinalHDL/VexiiRiscv.git", "fpu_internal", "b4e86579" if args.update_repo=="recommended" else None) NaxRiscv.git_setup("VexiiRiscv", ndir, "https://github.com/SpinalHDL/VexiiRiscv.git", "fpu_internal", "c330b794" if args.update_repo=="recommended" else None)