Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

vexriscv: allow user to use an external variant

This commit is contained in:
Florent Kermarrec 2019-03-15 18:16:25 +01:00
parent b04a756abb
commit 7b88980d06
1 changed files with 9 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
litex/soc/cores/cpu/vexriscv/core.py
View File

@ -18,6 +18,9 @@ class VexRiscv(Module, AutoCSR):
variant = "std_debug" if variant == "debug" else variant variant = "std_debug" if variant == "debug" else variant
variants = ("std", "std_debug", "lite", "lite_debug", "min", "min_debug") variants = ("std", "std_debug", "lite", "lite_debug", "min", "min_debug")
assert variant in variants, "Unsupported variant %s" % variant assert variant in variants, "Unsupported variant %s" % variant
self.platform = platform
self.variant = variant
self.external_variant = None
self.reset = Signal() self.reset = Signal()
self.ibus = ibus = wishbone.Interface() self.ibus = ibus = wishbone.Interface()
self.dbus = dbus = wishbone.Interface() self.dbus = dbus = wishbone.Interface()
@ -59,9 +62,6 @@ class VexRiscv(Module, AutoCSR):
if "debug" in variant: if "debug" in variant:
self.add_debug() self.add_debug()
# add verilog sources
self.add_sources(platform, variant)
def add_debug(self): def add_debug(self):
debug_reset = Signal() debug_reset = Signal()
@ -162,5 +162,11 @@ class VexRiscv(Module, AutoCSR):
vdir = os.path.join(os.path.abspath(os.path.dirname(__file__)), "verilog") vdir = os.path.join(os.path.abspath(os.path.dirname(__file__)), "verilog")
platform.add_source(os.path.join(vdir, cpu_filename)) platform.add_source(os.path.join(vdir, cpu_filename))
def use_external_variant(self, variant_filename):
self.external_variant = True
self.platform.add_source(variant_filename)
def do_finalize(self): def do_finalize(self):
if not self.external_variant:
self.add_sources(self.platform, self.variant)
self.specials += Instance("VexRiscv", **self.cpu_params) self.specials += Instance("VexRiscv", **self.cpu_params)