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cpu/microwatt: improve/fix XICS controller integration for variants with irq.

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This commit is contained in:
Florent Kermarrec 2020-12-30 12:24:48 +01:00
parent 0cba91022e
commit 7bcebf4cdd
2 changed files with 10 additions and 6 deletions
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11
litex/soc/cores/cpu/microwatt/core.py
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@ -16,7 +16,6 @@ from litex.soc.interconnect.csr import *
from litex.gen.common import reverse_bytes from litex.gen.common import reverse_bytes
from litex.soc.cores.cpu import CPU from litex.soc.cores.cpu import CPU
CPU_VARIANTS = ["standard", "standard+ghdl", "standard+irq", "standard+ghdl+irq"] CPU_VARIANTS = ["standard", "standard+ghdl", "standard+irq", "standard+ghdl+irq"]
class Microwatt(CPU): class Microwatt(CPU):
@ -108,16 +107,12 @@ class Microwatt(CPU):
# add vhdl sources # add vhdl sources
self.add_sources(platform, use_ghdl_yosys_plugin="ghdl" in self.variant) self.add_sources(platform, use_ghdl_yosys_plugin="ghdl" in self.variant)
# add XICS controller
if "irq" in variant:
self.add_xics()
def set_reset_address(self, reset_address): def set_reset_address(self, reset_address):
assert not hasattr(self, "reset_address") assert not hasattr(self, "reset_address")
self.reset_address = reset_address self.reset_address = reset_address
assert reset_address == 0x00000000 assert reset_address == 0x00000000
def add_xics(self): def add_xics(self, soc, soc_region_cls):
self.submodules.xics = XICSSlave( self.submodules.xics = XICSSlave(
platform = self.platform, platform = self.platform,
variant = self.variant, variant = self.variant,
@ -125,6 +120,10 @@ class Microwatt(CPU):
int_level_in = self.interrupt, int_level_in = self.interrupt,
endianness = self.endianness endianness = self.endianness
) )
xicsicp_region = soc_region_cls(origin=soc.mem_map.get("hostxicsicp", 0xc3ff0000), size=4096, cached=False)
xicsics_region = soc_region_cls(origin=soc.mem_map.get("hostxicsics", 0xc3ff1000), size=4096, cached=False)
soc.bus.add_slave(name="hostxicsicp", slave=self.xics.icp_bus, region=xicsicp_region)
soc.bus.add_slave(name="hostxicsics", slave=self.xics.ics_bus, region=xicsics_region)
@staticmethod @staticmethod
def add_sources(platform, use_ghdl_yosys_plugin=False): def add_sources(platform, use_ghdl_yosys_plugin=False):

5
litex/soc/integration/soc.py
View file

@ -895,6 +895,11 @@ class SoC(Module):
if hasattr(self.ctrl, "reset"): if hasattr(self.ctrl, "reset"):
self.comb += self.cpu.reset.eq(self.ctrl.reset) self.comb += self.cpu.reset.eq(self.ctrl.reset)
self.add_config("CPU_RESET_ADDR", reset_address) self.add_config("CPU_RESET_ADDR", reset_address)
# Specific Microwatt IROs integration FIXME (remove or provide generic integration method)
if isinstance(self.cpu, cpu.Microwatt) and "irq" in variant:
self.cpu.add_xics(self, SoCRegion)
# Add constants # Add constants
self.add_config("CPU_TYPE", str(name)) self.add_config("CPU_TYPE", str(name))
self.add_config("CPU_VARIANT", str(variant.split('+')[0])) self.add_config("CPU_VARIANT", str(variant.split('+')[0]))