link/cont: improve timing
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1170a1070b
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7ccc5f5274
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@ -14,6 +14,7 @@ class SATACONTInserter(Module):
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is_data = Signal()
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is_data = Signal()
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was_data = Signal()
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was_data = Signal()
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was_hold = Signal()
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change = Signal()
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change = Signal()
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self.comb += is_data.eq(sink.charisk == 0)
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self.comb += is_data.eq(sink.charisk == 0)
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@ -27,11 +28,10 @@ class SATACONTInserter(Module):
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If(~is_data,
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If(~is_data,
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last_primitive.eq(sink.data),
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last_primitive.eq(sink.data),
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),
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),
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was_data.eq(is_data)
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was_data.eq(is_data),
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was_hold.eq(last_primitive == primitives["HOLD"])
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)
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)
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]
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]
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was_hold = last_primitive == primitives["HOLD"]
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self.comb += change.eq(
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self.comb += change.eq(
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(sink.data != last_data) |
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(sink.data != last_data) |
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(sink.charisk != last_charisk) |
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(sink.charisk != last_charisk) |
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