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use max_count of 16 and clean up

This commit is contained in:
Florent Kermarrec 2014-12-23 23:19:48 +01:00
parent 74dd907503
commit 7df1d75dee
4 changed files with 8 additions and 8 deletions
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4
lib/sata/__init__.py
View File

@ -4,7 +4,7 @@ from lib.sata.transport import SATATransport
from lib.sata.command import SATACommand from lib.sata.command import SATACommand
class SATACON(Module): class SATACON(Module):
def __init__(self, phy, sector_size=512, max_count=8): def __init__(self, phy, sector_size=512, max_count=16):
self.sector_size = sector_size self.sector_size = sector_size
self.max_count = max_count self.max_count = max_count
@ -12,6 +12,6 @@ class SATACON(Module):
self.link = SATALink(phy) self.link = SATALink(phy)
self.transport = SATATransport(self.link) self.transport = SATATransport(self.link)
self.command = SATACommand(self.transport, sector_size=sector_size, max_count=max_count) self.command = SATACommand(self.transport, sector_size, max_count)
self.sink, self.source = self.command.sink, self.command.source self.sink, self.source = self.command.sink, self.command.source

2
lib/sata/command/__init__.py
View File

@ -102,7 +102,7 @@ class SATACommandRX(Module):
### ###
cmd_fifo = SyncFIFO(command_rx_cmd_description(32), 2) # Note: ideally depth=1 cmd_fifo = SyncFIFO(command_rx_cmd_description(32), 2) # Note: ideally depth=1
data_fifo = InsertReset(SyncFIFO(command_rx_data_description(32), sector_size*max_count//4, buffered=True)) data_fifo = InsertReset(SyncFIFO(command_rx_data_description(32), (sector_size*max_count//4), buffered=True))
self.submodules += cmd_fifo, data_fifo self.submodules += cmd_fifo, data_fifo
def test_type(name): def test_type(name):

6
platforms/kc705.py
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@ -128,9 +128,9 @@ def Platform(*args, toolchain="vivado", programmer="xc3sprog", **kwargs):
except ConstraintError: except ConstraintError:
pass pass
self.add_platform_command(""" self.add_platform_command("""
create_clock -name sys_clk -period 5 [get_nets sys_clk] create_clock -name sys_clk -period 10 [get_nets sys_clk]
create_clock -name sata_rx_clk -period 3.33 [get_nets sata_rx_clk] create_clock -name sata_rx_clk -period 6.66 [get_nets sata_rx_clk]
create_clock -name sata_tx_clk -period 3.33 [get_nets sata_tx_clk] create_clock -name sata_tx_clk -period 6.66 [get_nets sata_tx_clk]
set_false_path -from [get_clocks sys_clk] -to [get_clocks sata_rx_clk] set_false_path -from [get_clocks sys_clk] -to [get_clocks sata_rx_clk]
set_false_path -from [get_clocks sys_clk] -to [get_clocks sata_tx_clk] set_false_path -from [get_clocks sys_clk] -to [get_clocks sata_tx_clk]

4
targets/test.py
View File

@ -166,8 +166,8 @@ class TestDesign(UART2WB, AutoCSR):
UART2WB.__init__(self, platform, clk_freq) UART2WB.__init__(self, platform, clk_freq)
self.crg = _CRG(platform) self.crg = _CRG(platform)
self.sata_phy = SATAPHY(platform.request("sata_host"), clk_freq, host=True, speed="SATA2") self.sata_phy = SATAPHY(platform.request("sata_host"), clk_freq, speed="SATA2")
self.sata_con = SATACON(self.sata_phy, sector_size=512, max_count=8) self.sata_con = SATACON(self.sata_phy)
self.bist = SATABIST(self.sata_con) self.bist = SATABIST(self.sata_con)