Hardware/litex
1
0
Fork 0
mirror of https://github.com/enjoy-digital/litex.git synced 2025-01-04 09:52:26 -05:00
Code Issues Projects Releases Packages Wiki Activity

mibuild/xilinx: connect CE on reset synchronizer FFs

Browse source
This commit is contained in:
Sebastien Bourdeauducq 2014-08-06 23:51:50 +08:00
parent b124a98d92
commit 7ebf08db5e
1 changed files with 2 additions and 2 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

4
mibuild/xilinx_common.py
View file

@ -72,9 +72,9 @@ class XilinxAsyncResetSynchronizerImpl(Module):
rst1 = Signal() rst1 = Signal()
self.specials += [ self.specials += [
Instance("FDPE", p_INIT=1, i_D=0, i_PRE=async_reset, Instance("FDPE", p_INIT=1, i_D=0, i_PRE=async_reset,
i_C=cd.clk, o_Q=rst1), i_CE=1, i_C=cd.clk, o_Q=rst1),
Instance("FDPE", p_INIT=1, i_D=rst1, i_PRE=async_reset, Instance("FDPE", p_INIT=1, i_D=rst1, i_PRE=async_reset,
i_C=cd.clk, o_Q=cd.rst) i_CE=1, i_C=cd.clk, o_Q=cd.rst)
] ]
class XilinxAsyncResetSynchronizer: class XilinxAsyncResetSynchronizer: