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mibuild/xilinx: connect CE on reset synchronizer FFs
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1 changed files with 2 additions and 2 deletions
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@ -72,9 +72,9 @@ class XilinxAsyncResetSynchronizerImpl(Module):
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rst1 = Signal()
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self.specials += [
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Instance("FDPE", p_INIT=1, i_D=0, i_PRE=async_reset,
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i_C=cd.clk, o_Q=rst1),
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i_CE=1, i_C=cd.clk, o_Q=rst1),
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Instance("FDPE", p_INIT=1, i_D=rst1, i_PRE=async_reset,
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i_C=cd.clk, o_Q=cd.rst)
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i_CE=1, i_C=cd.clk, o_Q=cd.rst)
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]
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class XilinxAsyncResetSynchronizer:
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