cores/bitbang: Attach I2C init table directly to I2C cores and avoid global add_i2c_init_table SoC method.
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732529ecdf
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@ -22,6 +22,7 @@ class I2CMaster(Module, AutoCSR):
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Software get back SDA value with the read CSRStatus (_r).
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Software get back SDA value with the read CSRStatus (_r).
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"""
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"""
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init = []
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pads_layout = [("scl", 1), ("sda", 1)]
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pads_layout = [("scl", 1), ("sda", 1)]
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def __init__(self, pads=None):
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def __init__(self, pads=None):
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if pads is None:
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if pads is None:
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@ -51,6 +52,9 @@ class I2CMaster(Module, AutoCSR):
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i = self._r.fields.sda
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i = self._r.fields.sda
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)
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)
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def add_init(self, addr, init, init_addr_len=1):
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self.init.append((addr, init, init_addr_len))
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class I2CMasterSim(I2CMaster):
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class I2CMasterSim(I2CMaster):
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"""I2C Master Bit-Banging for Verilator simulation
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"""I2C Master Bit-Banging for Verilator simulation
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@ -77,6 +81,16 @@ class I2CMasterSim(I2CMaster):
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)
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)
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]
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]
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# I2C Master Init Collection ----------------------------------------------------------------------
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def collect_i2c_init(soc):
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i2c_init = []
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for name, obj in xdir(soc, True):
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if isinstance(obj, I2CMaster) and hasattr(obj, "init"):
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for addr, init, init_addr_len in obj.init:
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i2c_init.append((name, addr, init, init_addr_len))
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return i2c_init
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# SPI Master Bit-Banging ---------------------------------------------------------------------------
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# SPI Master Bit-Banging ---------------------------------------------------------------------------
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class SPIMaster(Module, AutoCSR):
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class SPIMaster(Module, AutoCSR):
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@ -204,7 +204,8 @@ class Builder:
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write_to_file(os.path.join(self.generated_dir, "csr.h"), csr_contents)
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write_to_file(os.path.join(self.generated_dir, "csr.h"), csr_contents)
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# Generate I2C command/value table
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# Generate I2C command/value table
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i2c_contents = export.get_i2c_header(self.soc.i2c_init)
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from litex.soc.cores.bitbang import collect_i2c_init
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i2c_contents = export.get_i2c_header(collect_i2c_init(self.soc))
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write_to_file(os.path.join(self.generated_dir, "i2c.h"), i2c_contents)
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write_to_file(os.path.join(self.generated_dir, "i2c.h"), i2c_contents)
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# Generate Git SHA1 of tools to git.h
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# Generate Git SHA1 of tools to git.h
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@ -174,9 +174,6 @@ class SoCCore(LiteXSoC):
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# Wishbone Slaves.
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# Wishbone Slaves.
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self.wb_slaves = {}
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self.wb_slaves = {}
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# I2C initialisation tables
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self.i2c_init = []
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# Modules instances ------------------------------------------------------------------------
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# Modules instances ------------------------------------------------------------------------
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# Add SoCController
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# Add SoCController
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@ -272,9 +269,6 @@ class SoCCore(LiteXSoC):
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def add_csr_region(self, name, origin, busword, obj):
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def add_csr_region(self, name, origin, busword, obj):
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self.csr_regions[name] = SoCCSRRegion(origin, busword, obj)
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self.csr_regions[name] = SoCCSRRegion(origin, busword, obj)
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def add_i2c_init_table(self, dev, i2c_addr, table, addr_len=1):
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self.i2c_init.append((dev, i2c_addr, table, addr_len))
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# Finalization ---------------------------------------------------------------------------------
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# Finalization ---------------------------------------------------------------------------------
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def do_finalize(self):
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def do_finalize(self):
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